Proceedings Article10.1109/ASAP.1990.145467
The RAP: a ring array processor for layered network calculations
Nelson Morgan,James Beck,Philip D. Kohn,Jeff A. Bilmes,Eric Allman,J. Beer +5 more
- 05 Sep 1990
- pp 296-308
35
TL;DR: The authors have designed and implemented a ring array processor, RAP, for fast implementation of layered neural network algorithms, a multi-DSP system targeted at continuous speech recognition using connectionist algorithms.
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Abstract: The authors have designed and implemented a ring array processor, RAP, for fast implementation of layered neural network algorithms. The RAP is a multi-DSP system targeted at continuous speech recognition using connectionist algorithms. Four boards, each with four Texas Instruments, TMS 320C30 DSPs, serve as an array processor for a 68020-based host running a real-time operating system. The overall system is controlled from a Sun workstation via the Ethernet. Each board includes 16 MB of dynamic memory (expandable to 64 MB) and 1 MB of fast static RAM. Theoretical peak performance is 128 MFLOPS/board, and test runs with the first working board show a sustained throughput of roughly one-third to one-half of this for algorithms of interest. Software development is aided by a Sun workstation-based command interpreter, tools from the standard C environment and a library of matrix and vector routines. >
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Citations
SYNAPSE: a neurocomputer that synthesizes neural algorithms on a parallel systolic engine
TL;DR: The proposed neurocomputer concept is adaptable to the applicational domain in terms of processing power, memory, and flexibility and designed to execute preprocessing operations such as DCT and convolution in a favorable manner.
90
CDNN: a context dependent neural network for continuous speech recognition
Hervé Bourlard,Nelson Morgan,Chuck Wooters,Steve Renals +3 more
- 23 Mar 1992
TL;DR: It is shown how, without any simplifying assumptions, one can estimate likelihoods for context-dependent phonetic models with nets that are not substantially larger than context-independent MLPs.
The Ring Array Processor: a multiprocessing peripheral for connectionist applications
TL;DR: The motivation for the RAP is described and how the architecture matches the target algorithm is shown, which is to reduce peak performance on the error back-propagation algorithm to about 50% of a linear speedup.
75
A new classification approach for neural networks hardware: from standards chips to embedded systems on chip
TL;DR: A new classification approach for classification of neural networks hardware that takes into account most of consensual elements in one hand and in the other hand it takes into consideration the evolution of the design technology of integrated circuits and the design techniques.
68
Design of a 1st Generation Neurocomputer
U. Ramacher,J. Beichter,W. Raab,J. Anlauf,N. Bruls,U. Hachmann,M. Wesseling +6 more
- 01 Jan 1991
TL;DR: The proposed neurocomputer concept is sizeable independently to the applicational domain in terms of processing power, memory size and flexibility, and is designed for throughputs that enable the user to access real-world applications in reasonable time.
55
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