The MIPS-X RISC Microprocessor
Paul Chow
- 01 Jan 1989
33
TL;DR: This document discusses the architecture of the MIPS-X Compiler System, the hardware and software behind it, and some of the techniques used to develop and implement this system.
read more
Abstract: 1 Introduction.- 2 Architecture.- 3 The Compiler System.- 4 A Hardware Overview.- 5 The Execute Engine.- 6 Instruction Fetch Hardware.- 7 The External Interface.- A Exception Handling.- A.1 Interrupts.- A.2 Trap On Overflow.- A.3 Trap Instructions.- B Integer Multiplication and Division.- B.1 Multiplication and Division Support.- B.2 Multiplication.- B.3 Division.- C Opcode Map.- C.1 OP Field Bit Assignments.- C.2 Comp Func Field Bit Assignments.- C.3 Opcode Map of All Instructions.- D MIPS-X Revision 1 and 2 Pin Numbers.- D.1 Pin Mapping for Probe Card and Funsim.- D.2 Pin Map for 144 Pin PGA.- E Revision 1 and Revision 2 Differences.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
An area model for on-chip memories and its application
TL;DR: An area model suitable for comparing data buffers of different organizations and arbitrary sizes is described and it is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes.
Area efficient architectures for information integrity in cache memories
Seongwoo Kim,Arun K. Somani +1 more
- 01 May 1999
TL;DR: This work focuses on transient fault tolerance in primary cache memories and develops new architectural solutions, to maximize fault coverage when the budgeted silicon area is not sufficient for the conventional configuration of an error checking code.
112
Exploring optimal cost-performance designs for Raw microprocessors
Csaba Andras Moritz,Donald Yeung,Anant Agarwal +2 more
- 15 Apr 1998
TL;DR: This paper presents an analytical framework using which designers can reason about the design space of Raw microprocessors, based on an architectural model and a VLSI cost analysis, and uses an optimization process to identify designs that will execute these applications most cost-effectively.
46
Analysis of power supply networks in VLSI circuits
Don Stark
- 01 Mar 1991
TL;DR: Ariel as mentioned in this paper is a CAD tool that helps VLSI designers analyze power supply noise and current densities in chip power supply networks by using a linear solver to determine voltage drops and current density along the supply lines.
44
Partial resolution in branch target buffers
Barry Fagin,Kathryn Russell +1 more
- 01 Dec 1995
TL;DR: This analysis of the relationship between the number of tag bits in a branch target buffer and prediction accuracy, based on dynamic simulations of the SPECINT92 benchmark suite, suggests that existing microprocessors can achieve substantial area savings in BTB tag storage by employing partial resolution.
40
Related Papers (5)
John L. Hennessy,David A. Patterson +1 more
- 01 Dec 1989
Paul Chow
- 01 Jan 1989
YunZhu Xiang,YueHua Ding +1 more
- 25 Sep 2008