The computer handbook

TL;DR: It is shown that DDA speed and accuracy can be greatly improved by using increment word lengths which are approximately one-half the length of integrand registers providing that integration formulas more accurate than Euler integration are used.

TL;DR: A compact analog computer is described and its use in electronic engineering teaching laboratories to develop student understanding of applications in analog electronics, electronic components, engineering mathematics, control engineering, safe laboratory and workshop practices, circuit construction, testing, and maintenance.

TL;DR: In this paper, the social hierarchy developed in conjunction with the division of labor among workers of quite different levels of mathematical expertise was considered, and the means by which such tables were constructed.

TL;DR: A variable high-speed incremental computer that adopts the basic concept underlying a digital differential analyzer (DDA) and includes the following features: floating-point arithmetic, a word-length transfer with the elimination of a residue (R) register, multibit multiplication, and a flexible software scheme of interconnections that includes the use of a stack to avoid redundant operations.

TL;DR: It is shown that DDA speed and accuracy can be greatly improved by using increment word lengths which are approximately one-half the length of integrand registers providing that integration formulas more accurate than Euler integration are used.

TL;DR: A compact analog computer is described and its use in electronic engineering teaching laboratories to develop student understanding of applications in analog electronics, electronic components, engineering mathematics, control engineering, safe laboratory and workshop practices, circuit construction, testing, and maintenance.

TL;DR: A variable high-speed incremental computer that adopts the basic concept underlying a digital differential analyzer (DDA) and includes the following features: floating-point arithmetic, a word-length transfer with the elimination of a residue (R) register, multibit multiplication, and a flexible software scheme of interconnections that includes the use of a stack to avoid redundant operations.

TL;DR: A proposed new parallel architecture, Torus Integrated Machine (TIM) which is designed to incorporate physical compactness, dedicated analog hardware and programmability, and could be an ideal testbed for early-vision algorithms.