The active NPC converter and its loss-balancing control

TL;DR: The losses balance of 5L-TNPC inverters is analyzed and a circuit based on hybrid SiC and Si devices is proposed to improve the performance.

TL;DR: This study proposes an improved SVPWM strategy to balance losses in three-level ANPC converters, reducing switch action and unbalance by 16.75% and 6.48% respectively, enhancing converter capacity and lifespan in applications like motor speed regulation and high-voltage transmission.

Abstract: In recent years, interest in highly efficient and compact power converters in power electronics applications has been increasing day by day. In this study, a SiC MOSFET-based 3-level (3L) T-Type inverter (TNPC) is proposed to obtain a high-efficiency and compact converter. Considering the MSCSM120HRM163AG-SiC-MOSFET intelligent power modules (IPM) developed by Microchip for 3L T-Type inverter, the power losses of a 3-phase 3-level T-Type inverter are calculated in MATLAB environment. To demonstrate the efficiency of SiC MOSFET based T-Type Inverter, a 3-phase 3L T-Type inverter feeding a vector-controlled 3-phase PMSM is simulated using MATLAB/Simulink and Simscape blocks. In the simulation, the PMSM is operated at different speed references under almost full load (42.09 Nm). While the PMSM operates at 3000 rpm under 40Nm load, the voltage-current waveforms of the SiC MOSFETs in the T-Type inverter are obtained. Using these waveforms and the data from the data sheets of the IPMs, the power losses of the 3L TNPC inverter are calculated for different switching frequencies. The Space Vector PWM method used to generate 50 kHz PWM signals for the 3L T-Type inverter also ensures that the dc-link capacitor voltages remain balanced. In addition, the variations of line-to-line voltage and dc-link capacitor voltages of the inverter and the variations of speed, torque, rotor position, d-q currents, and stator currents of the PMSM are given.

TL;DR: An open-loop NP potential balancing control for 5L-NPC full-bridge grid-tied inverters (FB-GCIs) is proposed and experimental results validate the feasibility and effectiveness of the proposed control method.

TL;DR: In this article, a neutral-point-clamped PWM inverter composed of main switching devices which operate as switches for PWM and auxiliary switching devices to clamp the output terminal potential to the neutral point potential has been developed.

TL;DR: In this paper, a multilevel commutation cell is introduced for high-voltage power conversion, which can be applied to either choppers or voltage-source inverters and generalized to any number of switches.

TL;DR: In this paper, the fundamental limitations of the neutral-point voltage balancing problem for different loading conditions of three-level voltage source inverters are explored and a new model in the DQ coordinate frame is developed as a means to investigate theoretical limitations and to offer a more intuitive insight into the problem.