Journal Article10.1109/TC.2013.206
Testing Open Defects in Memristor-Based Memories
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TL;DR: The fault analysis reveals that unique faults occur in addition to some conventional memory faults, and the detection of such unique faults cannot be guaranteed with just the application of traditional march tests, so a new Design-for-Testability (DfT) concept is presented to facilitate the Detection of the unique faults.
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Abstract: Memristor-based memory technology, also referred to as resistive RAM (RRAM), is one of the emerging memory technologies potentially to replace conventional semiconductor memories such as SRAM, DRAM, and flash. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques, and reliability improvement. However, research on (manufacturing) test for yield and quality improvement is still in its infancy stage. This paper presents fault analysis and modeling for open defects based on electrical simulation, introduces fault models, and proposes test approaches for RRAMs. The fault analysis reveals that unique faults occur in addition to some conventional memory faults, and the detection of such unique faults cannot be guaranteed with just the application of traditional march tests. The paper also presents a new Design-for-Testability (DfT) concept to facilitate the detection of the unique faults. Two DfT schemes are developed by exploiting the access time duration and supply voltage level of the RRAM cells, and their simulation results show that the fault coverage can be increased with minor circuit modification. As the fault behavior may vary due to process variations, the DfT schemes are extended to be programmable to track the changes and further improve the fault/defect coverage.
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Citations
TiO2-based memristors and ReRAM: materials, mechanisms and models (a review)
TL;DR: In this paper, the state-of-the-art for resistive random access memory (ReRAM) and memristor nonvolatile memory (MIMO) is summarized.
175
Inspection and Classification of Semiconductor Wafer Surface Defects Using CNN Deep Learning Networks
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A general memristor-based pulse coupled neural network with variable linking coefficient for multi-focus image fusion
Zhekang Dong,Zhekang Dong,Chun Sing Lai,Chun Sing Lai,Chun Sing Lai,Donglian Qi,Zhao Xu,Chaoyong Li,Shukai Duan +8 more
TL;DR: A novel Memristor crossbar array with its corresponding peripheral circuits is proposed, which is able to construct a general memristor-based PCNN (MPCNN) with variable linking coefficient, and has superior performances in terms of image quality and fusion effect compared to several existing algorithms.
68
Device-Aware Test: A New Test Approach Towards DPPB Level
Moritz Fieback,Lizhou Wu,Guilherme Cardoso Medeiros,Hassen Aziza,Siddharth Rao,Erik Jan Marinissen,Mottaqiallah Taouil,Said Hamdioui +7 more
- 09 Nov 2019
TL;DR: The results show that the proposed approach is able to sensitize faults for defects that are not detected with the traditional approach, meaning that the latter cannot lead to high-quality test solutions as required for a defective part per billion (DPPB) level.
Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays
TL;DR: This work presents a comprehensive analysis of fault models which represent both parametric variations as well as defects (opens and shorts) in STT MRAM.
63
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