Proceedings Article10.1109/ICMTS.2003.1197384
Test time reduction methods for yield test structures
Christopher Hess,H. Read,J. Ren,Larg Weiland,Jianjun Cheng,Chock Gan,H. Karbasi,S. Winters +7 more
- 17 Mar 2003
- pp 3-69
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TL;DR: This paper will present methods how test structures can be redesigned to better support testing and modified test algorithms that will significantly reduce the test time by 50% and more, which will accelerate data analysis and increases efficient use of parametric test systems.
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Abstract: Complexity of integrated circuits has led to hundreds of millions of transistors, wiring lines, and layer to layer via connections on every chip. To allow accurate yield evaluation, it is required that process characterization test chips grow in complexity as well which has let to a significant bottleneck in testing them. Wafers that could be tested in less than two hours in a 0.35/spl mu/m technology now require 10 hours and more in a 0.13/spl mu/m technology. This paper will present methods how test structures can be redesigned to better support testing. Based on those we will present modified test algorithms that will significantly reduce the test time by 50% and more, which will accelerate data analysis and increases efficient use of parametric test systems.
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Citations
Short-flow test chip utilizing fast testing for defect density monitoring in 45nm
M. Karthikeyan,W. Cote,Louis V. Medina,Ernesto Shiling,A. Gasasira,A. Henning,W. Ferrante,M. Craig,T. Merbeth +8 more
- 24 Mar 2008
TL;DR: In this article, a 45 nm short-flow test chip was designed and is currently used to improve defect-limited yield, where the DC test structures are tested in parallel mode on a functional test platform, resulting in a 5x reduction in test time over conventional parametric testing.
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Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement
M. Karthikeyan,Louis V. Medina,Ernesto Shiling +2 more
- 14 Apr 2009
TL;DR: In this article, the authors describe the development and use of various test structures for 32nm yield enhancement, which are tested in parallel mode on a functional tester using special V/I and Pico-Amp measurement cards.
6
Contact Chains for FinFET Technology Characterization
TL;DR: A new type of test structure, so-called gated contact chains, developed for contact process characterization in FinFET technologies is described, which contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance.
4
32nm yield learning using efficient parallel-test structures
M. Karthikeyan,Louis V. Medina,Ernesto Shiling,David A. Kiesling +3 more
- 11 Jul 2010
TL;DR: The test structures described herein help accelerate yield learning by enabling characterization of yield-loss mechanisms and rapid evaluation of yield improvement actions.
2
Gated contact chains for process characterization in FinFET technologies
Tomasz Brozek,Stephen Lam,Shia Yu,Mike Pak,Tom Liu,Rakesh Valishayee,Nobuharu Yokoyama +6 more
- 24 Mar 2014
TL;DR: Examples of test structures for contact process development for FinFET technologies with series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance are described.
2
References
Integrated circuit yield management and yield analysis: development and implementation
C.H. Stapper,R.J. Rosner +1 more
TL;DR: In this article, the authors proposed a yield management approach based on defect density learning to determine the contamination levels for clean rooms and process equipment, which allows for a systematic allocation of resources.
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Fast extraction of defect size distribution using a single layer short flow NEST structure
TL;DR: In this paper, a novel NEST structure was proposed to improve accuracy of electrically based determination of defect densities and defect size distributions, where many nested serpentine lines were placed within a single layer only.
Passive multiplexer test structure for fast and accurate contact and via fail rate evaluation
Christopher Hess,Brian E. Stine,Larg Weiland,Todd Mitchell,M.P. Karnett,K. Gardner +5 more
- 08 Apr 2002
TL;DR: A Passive Multiplexer Array of via chains, which breaks up a huge contact/via chain in many individually measurable sub-chains, which better supports failure analysis, since it is faster to locate a faulty contact or via.
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