Patent
Test structure for automatic dynamic negative-bias temperature instability testing
Chew Hoe Ang,Gang Chen,Shyue Seng Tan +2 more
- 10 Jun 2004
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TL;DR: In this article, the authors describe a test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI), which consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test.
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Abstract: The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUTs).
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Citations
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13
References
Dynamic NBTI of PMOS transistors and its impact on device lifetime
Gang Chen,K.Y. Chuah,Meng Li,D.S.H. Chan,Chew Hoe Ang,Jia Zhen Zheng,Yunye Jin,Dim-Lee Kwong +7 more
- 13 May 2003
TL;DR: In this article, the authors demonstrate that the interface traps generated under NBTI stressing in a p-MOSFET are subsequently passivated when the gate to drain voltage switches to positive (corresponding to the low output state of the inverter).
206
Patent
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Mano D. Judd,Thomas D. Monte,Donald G. Jackson,Gregory A. Maca +3 more
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Jonathan H. Liu
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Line monitoring of negative bias temperature instabilities by hole injection methods
Giuseppe La Rosa,Fernando Guarin,Stewart E. Rauch +2 more
- 25 Sep 2000
TL;DR: In this paper, a hole injection method is selected that produces approximately the same gate oxide degradation as the NBTI under test, and a correlation is established between the degradation and device shifts due to the selected hole injection degradation method.
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