Patent
Test pattern address generator
Robert D. Catiller
- 26 May 1981
16
TL;DR: In this paper, a test pattern generator is used for generating a series of address signals such as for exercising an integrated circuit memory, which is used to trigger a three-stage counting circuit and also a circuit array of exclusive OR gates.
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Abstract: A test pattern generator is used for generating a series of address signals such as for exercising an integrated circuit memory. Master reference clock means are used to trigger a three stage counting circuit and also a circuit array of exclusive OR gates. The outputs of the stages of the counter provide individual inputs to each of the exclusive OR gates. The array of exclusive OR gates is arranged so that each exclusive OR gate has an output line which provides one bit of information for the address signals. The combination of the outputs of the OR gates forms a parallel bus which carries the address signals to be applied to the integrated circuit memory. The circuit generates a specialized address pattern in which the original address generated is complemented, then incremented on a series of increment-complement actions so that all combinations of the row and column drivers in the integrated circuit memory are exercised.
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Citations
Patent
Memory test method and apparatus
Donald W. Smelser
- 11 May 1988
TL;DR: In this paper, a method and apparatus for memory testing is described, where a first pattern of data is written into the memory in a pseudo-random address sequence determined by an address generator.
67
Patent
Testing and diagnostic device for digital computers
Arnold Dipl Ing Blum
- 19 Apr 1984
TL;DR: In this paper, an EDP system is used for error testing and diagnostics in EDP systems, particular storage elements are connected to form an addressable matrix which is coupled to a maintenance and service processor or an external tester through the system bus.
61
Patent
Integrated circuit with memory self-test
Duane Rodney Aadsen,Sunil Kumar Jain,Charles E. Stroud +2 more
- 02 Oct 1986
TL;DR: In this paper, a memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word.
52
Patent
Method and apparatus for testing integrated circuit memories
George D. Green,William C. Mullauer +1 more
- 05 Aug 1988
TL;DR: In this article, a random sequencer is used to generate a pseudo-random data bit pattern to be written into the cells of a DRAM chip, which can be used to test the functionality and maximum operating speed of the DRAM.
47
Patent
System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module
Mitchell A. Bauman,Roger L. Gilbertson,EuGene A. Rodi +2 more
- 31 Dec 1998
TL;DR: In this paper, a data pattern generator is coupled to a corresponding one of the address generators to receive data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator.
46
References
Patent
Logic chip test system with path oriented decision making test pattern generator
Prabhakar Goel
- 20 Nov 1978
TL;DR: In this article, a path oriented decision-making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines.
44
Patent
Test generator for random access memories
Michael K. Benton,Suresh H. Sangani +1 more
- 24 Oct 1978
TL;DR: In this article, the authors describe electronic circuits for detecting functional failures of random access memory (RAM) devices, which generate a bit pattern sequence for each memory address location and write the pattern into the memory.
43
Patent
Method of measuring the memory address access time (AAT) utilizing a data recirculation technique, and a tester for accomplishing same
Jacky Henri Jocotton,Bernard Vanoudheusden +1 more
- 18 Apr 1980
TL;DR: In this article, a method and apparatus for measuring the memory address access time (AAT) of RAM and ROS memories is presented, which is based on the data recirculation technique.
18
Patent
Pattern generation system
Dieter E. Staiger
- 04 Aug 1978
TL;DR: In this article, a pattern generator with a programmable product cycle timer is described, in which a pulse train can be repeated or switched from a first pulse frequency to a second pulse frequency without the usual transient switching periods between pulses.
11
Patent
Information collection and storage system with memory test circuit
Arlan J. Lyhus
- 30 Mar 1979
TL;DR: In this article, an information recording system has an electrical circuit for counting serially occurring pulses, the number of which is indicative of certain information, a memory storage unit adapted to be removably plugged into said circuit for connection thereto and having a memory containing a multiplicity of binary bit storage cells or character locations for storing binary data resulting from the counting of the pulses, a display device, or other suitable means rendered effective by the interrogating means for signalling an operator whenever the logic state in any one of the character locations fails to conform to the preselected code.
10
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