Template based asynchronous design

TL;DR: This paper presents the design of a channel-based asynchronous sequential decoder implemented with quasi-delay-insensitive templates and highlights the introduction of a standard-cell library and back-end design flow for asynchronous designs based on precharged half buffer (PCHB) templates.

TL;DR: In this article, a multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking.

TL;DR: In this article, les operateurs regionaux de moyen niveau sont un maillon essentiel de la chaine de traitement de l'image.

TL;DR: A synthesis of the main characteristics of the different classes of asynchronous digital circuits is presented and the techniques used in the style ofynchronous digital design are described.

TL;DR: This book explains coding for Reliable Digital Transmission and Storage using Trellis-Based Soft-Decision Decoding Algorithms for Linear Block Codes and Convolutional Codes, and some of the techniques used in this work.

TL;DR: Textbook on communication engineering emphasizing random processes, information and detection theory, statistical communication theory, applications, etc.

TL;DR: This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs), and develops a number of analytical results which establish the equivalence between the static structure of nets and their underlying firing sequence semantics.

TL;DR: In this paper, the authors present an overview of the design of Verilog HDLs and its application in computer aided digital design (CADD), including the following: 1. Hierarchical Modeling Concepts.