Patent
Techniques for enforcing control flow integrity using binary translation
Koichi Yamada,Palanivelrajan Shanmugavelayutham,Sravani Konda +2 more
- 23 Dec 2014
32
TL;DR: In this article, the authors present a method to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target addresses in a table in memory.
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Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
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Citations
Patent
Reuse of decoded instructions
Douglas C. Burger,Aaron L. Smith +1 more
- 26 Jun 2015
TL;DR: In this paper, the authors present a system for reusing fetched and decoded instructions in block-based processor architectures, where the instruction scheduler can adjust a mapping of instruction blocks in flight so that the given instruction block is re-executed on the first processor core without re-fetching the given instructions.
15
Patent
Verifying branch targets
Douglas C. Burger,Aaron L. Smith,Jan Gray +2 more
- 26 Jun 2015
TL;DR: In this article, an approach and methods for implementing bad jump detection in block-based processor architectures are described. But they do not specify a specific implementation of the bad jump detector, only a control unit that checks whether a branch signal is received from one of the instruction blocks.
13
Patent
Decoupled processor instruction window and operand buffer
Douglas C. Burger,Aaron Smith,Jan Gray +2 more
- 26 Jun 2015
TL;DR: In this article, a processor core in an instruction block-based microarchitecture is configured so that an instruction window and operand buffers are decoupled for independent operation in which instructions in the block are not tied to resources such as control bits and operands that are maintained in the operand buffer.
12
Patent
Mapping instruction blocks based on block size
Douglas C. Burger,Aaron Smith,Jan Gray +2 more
- 26 Jun 2015
TL;DR: A processor core in an instruction block-based microarchitecture utilizes instruction blocks having headers that include an index to a size table that may be expressed using one of memory, register, logic, or code stream as discussed by the authors.
10
Patent
Age-based management of instruction blocks in a processor instruction window
Douglas C. Burger,Aaron L. Smith,Jan Gray +2 more
- 26 Jun 2015
TL;DR: In this paper, a processor core in an instruction block-based microarchitecture includes a control unit that explicitly tracks instruction block state including age or priority for current blocks that have been fetched from an instruction cache.
10
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