Table based data speculation circuit for parallel processing computer

TL;DR: In this paper, code blocks of instructions are transformed from the original instruction set architecture to a new architecture by an instruction stream transformation unit, and the transformed code blocks are then cached in the instruction stream cache.

TL;DR: In this paper, the conflict data characterises previously encountered conflicts between processing transactions and the scheduling is performed such that a candidate processing transaction will not be scheduled if conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transactions.

TL;DR: In this paper, a load store dependency predictor may include a table for storing entries for load-store pairs that have been found to be dependent and execute out of order, each entry in the table includes a counter to indicate a strength of the dependency prediction.

TL;DR: In this article, a store set ID table (SSIT) is used to index store sets and the pointer to the last unexecuted store instruction is used for each store set.

TL;DR: In this article, an out-of-order execution of load and store instructions is dynamically controlled by detecting a store violation condition and avoiding the penalty of a pipeline recovery process by using a unique store barrier cache which is used to dynamically predict whether or not a violation condition is likely to occur and, if so, to restrict the issue of instructions to the load/store unit until the store instruction has been executed.

TL;DR: In this paper, a parallel processing control apparatus comprises processing blocks each providing an equal function and incorporating pipeline operation units, a status register for storing statuses of the processing blocks, an instruction feeder for simultaneously allocating instructions to the processors, and a write controller for selecting a processing block whose status is to be written in the status register.