Systematic algorithm mapping for multidimensional systolic arrays

TL;DR: The circuit goal was to maximize throughput and minimize the use of the FPGA LUT and register logic fabric, and comparison results from seven different designs showed increases in throughput per logic cell up to 181% with an average improvement of 94%.

TL;DR: The authors present a technique for transforming DSP (digital signal processing) algorithms to a form suitable for multidimensional systolic array implementation to speed up computation without much increase in area requirement.

TL;DR: This dissertation presents a system-level approach to localize computation and communication in an efficient computing platform and presents a new area I/O systolic architecture to exploit the physical locality of planar data streams by processing the data where it falls.

TL;DR: The method presented here increases the available degree of parallelism and thus improves the time complexity of systolic computations.

TL;DR: The basic principle of systolic architectures is reviewed and it is explained why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.

TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.

TL;DR: This paper is concerned with the mapping of cyclic loop algorithms into special-purpose VLSI arrays and the mapping procedure is based on the mathematical transformations of index sets and data dependence vectors.