Proceedings Article10.1109/ACSSC.2003.1292229
System design of a low-power I/O link
S.R. Sridhara,Ganesh Balamurugan,Naresh R. Shanbhag +2 more
- 01 Dec 2003
- Vol. 2, pp 1468-1472
2
TL;DR: A detailed analysis of the system design choices available for low-power high-speed I/O link transceivers shows that, for a typical 20" intersymbol interference dominated link, transmit pre-emphasis in combination with 4-PAM results in 75 data rates.
read more
Abstract: In this paper, we present a detailed analysis of the system design choices available for low-power high-speed I/O link transceivers. Using the transceiver power dissipation as the metric, we compare three equalization schemes (linear equalizer, decision-feedback equalizer, and transmit pre-emphasis) in combination with three pulse amplitude modulation (PAM) schemes (2-PAM, 4-PAM, and 8-PAM). The input signal levels and the filter lengths in the equalizer are chosen to minimize the power dissipation while meeting a bit error rate constraint. We show that, for a typical 20" intersymbol interference dominated link, transmit pre-emphasis in combination with 4-PAM results in 75 data rates.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Voltage mode line driver and pre-emphasis circuit
Khaldoon Abugharbieh,Mark J. Marlett +1 more
- 28 May 2010
TL;DR: In this paper, a voltage-mode line driver circuit is provided for transmitting a differential signal, which includes a first voltage swing circuit having an input coupled to receive an input signal and an output coupled to a first transmission line.
12
A 33mW 12.5Gbps BiCMOS transmitter for high speed backplane applications
TL;DR: This paper describes a 12.5Gbps voltage mode transmitter with a high speed signal conditioning capability using a linear equalizer that is followed by a power efficient output stage, which achieves pre-emphasis at very low power consumption.
4
References
•Book
Digital Systems Engineering
William J. Dally,John W. Poulton +1 more
- 28 Jun 1998
TL;DR: The techniques described in this book, which were once used only in supercomputers, are now essential to the correct and efficient operation of any type of digital system.
868
Low-power area-efficient high-speed I/O circuit techniques
TL;DR: A 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/ of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS technology is presented.
A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver
TL;DR: In this paper, an 8-Gb/s 0.3/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects.
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS
TL;DR: This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors.
151
Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver
Vladimir Stojanovic,Georgios Ginis,Mark Horowitz +2 more
- 07 Aug 2002
TL;DR: In this paper, a transmit pre-emphasis filter for a multi-level transceiver making use of time division multiplexing (TDM) is described, and the design of the preemphasis filter is shown to be a non-convex optimization problem whose optimal solution is very difficult to obtain.