System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module

TL;DR: In this paper, a data pattern generator is coupled to a corresponding one of the address generators to receive data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator.

Abstract: A system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. A plurality of memory exerciser testers are provided, one for each of the plurality of memory banks. Each of the memory exerciser testers includes an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner, while each of the address generators concurrently addresses a different one of the memory banks. A data pattern generator is coupled to a corresponding one of the address generators to receive a data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator. The data pattern generator outputs a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal. A plurality of address initialization registers are provided, one for each of the plurality of exerciser testers. Each of the address initialization registers stores an initial memory bank address for one of the memory banks such that each of the address generators is preset to initially address a different one of the memory banks. In this manner, each memory bank is addressed by a different one of the address generators at any given time, which provides for concurrent testing of all memory banks and memory interfaces.