Patent
System and method for a software controlled cache
Peter C. Damron
- 29 Sep 2000
22
TL;DR: In this paper, a cache address space is provided for each cache and special instructions are generated and inserted into the program to directly control caching of data in at least one of the cache-lines.
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Abstract: A system and method are provided for improved handling of data in a cache memory system ( 105 ) for caching data transferred between a processor ( 110 ) capable of executing a program and a main-memory ( 115 ). The cache memory system ( 105 ) has at least one cache ( 135 ) with several cache-lines ( 160 ) capable of caching data therein. In the method, a cache address space is provided for each cache ( 135 ) and special instructions are generated and inserted into the program to directly control caching of data in at least one ofthe cache-lines ( 160 ). Special instructions received in the cache memory system ( 105 ) are then executed to cache the data. The special instructions can be generated by a compiler during compiling of the program. Where the cache memory system ( 105 ) includes a set-associative-cache having a number of sets each with several cache-lines ( 160 ), the method can further include the step of determining which cache-line in a set to flush to main-memory ( 115 ) before caching new data to the set.
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Citations
Patent
Software Pipelining On A Network On Chip
Eric O. Mejdrich,Paul E. Schardt,Robert A. Shearer +2 more
- 12 Nov 2007
TL;DR: Memory sharing in a software pipeline on a network on chip (NOC) is discussed in this paper, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers.
71
Patent
Apparatus and method for partitioning a shared cache of a chip multi-processor
Matthew Mattina,Antonio Juan-Hormigo,Joel Emer,Matas-Navarro Ramon +3 more
- 30 Jun 2004
TL;DR: In this article, a method and apparatus for partitioning a shared cache of a chip multi-processor are described, which includes a request of a cache block from system memory if a cache miss within a share cache is detected according to a received request from a processor.
61
Patent
Reducing data speculation penalty with early cache hit/miss prediction
Jih-Kwon Peir,Konrad K. Lai +1 more
- 01 May 2002
TL;DR: In this paper, a processor may use a cache hit/miss prediction table (CPT) to predict whether a load will hit or miss and use this information to schedule dependent instructions in the instruction pipeline.
53
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Russell D. Hoover,Jon K. Kriegel,Eric O. Mejdrich,Robert A. Shearer +3 more
- 15 Feb 2008
TL;DR: In this article, the authors describe a network on chip (NOC) that includes integrated processor (IP) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller.
52
Patent
Network on chip with partitions
Russell D. Hoover,Eric O. Mejdrich,Paul E. Schardt,Robert A. Shearer +3 more
- 27 Nov 2007
TL;DR: A network on chip (NOC) as discussed by the authors includes integrated processor (IP) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller.
52
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