Journal Article10.1109/TC.1981.6312184
Synchronization and voting
24
TL;DR: This correspondence presents voter designs for three different signaling conventions (transition, level, and pulse) and the issue of improved voter performance is also addressed.
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Abstract: This is an elaboration of the paper `Synchronization and matching in redundant systems' by Davies and Wakerly (ibid., vol.27, p.531-9, 1978). The design of voters for synchronization is strongly dependent on the signaling convention used. This correspondence presents voter designs for three different signaling conventions (transition, level, and pulse). The issue of improved voter performance is also addressed.
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Citations
Patent
Fault-tolerant computer system with online recovery and reintegration of redundant components
Douglas E. Jewett,Tom Bereiter,Bryan Vetter,Randall G. Banton,Richard W. Cutts,Donald C. Westbrook,Krayn W. Fey,John Posdro,Kenneth C. Debacker,Nikhil A. Mehta +9 more
- 08 Jan 1999
TL;DR: In this article, a fault-tolerant configuration of multiple identical CPUs executing the same instruction stream, with multiple identical memory modules in the address space of the CPUs storing duplicates of the same data, is presented.
360
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Multiple processor system having shared memory with private-write capability
Richard W. Cutts,Nikhil A. Mehta,Douglas E. Jewett +2 more
- 13 Dec 1988
TL;DR: In this paper, a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple identical memory modules in the address space of the CPUs storing duplicates of the same data.
185
Patent
Method and apparatus for synchronizing a plurality of processors
Robert W. Horst
- 09 Dec 1992
TL;DR: In this article, a synchronizing system for a plurality of processors is presented, where each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state.
142
Patent
Multiprocessor system with each processor executing the same instruction sequence and hierarchical memory providing on demand page swapping
Douglas E. Jewett
- 24 Nov 1992
TL;DR: In this paper, a hierarchical virtual memory management scheme is proposed to keep the most-used data in the local memory, page swapping with disk memory is through the global memory; the globalmemory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory.
77
Patent
Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are synchronized upon each voted access to two memory modules
Richard W. Cutts,Peter C. Norwood,Kenneth C. Debacker,Nikhil A. Mehta,Douglas E. Jewett,John David Allison,Robert W. Horst +6 more
- 06 Mar 1991
TL;DR: In this paper, a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical self-checking memory modules storing duplicates of the same data.
73
References
Synchronization and Matching in Redundant Systems
TL;DR: A novel mutual feedback technique, called "synchronization voting," is introduced that does not have vulnerability to common-point failures and is described in the appendix—a fault-tolerant crystal-controlled clock.
124
A case study of C.mmp, Cm * , and C.vmp: Part I—Experiences with fault tolerance in multiprocessor systems
D.P. Siewiorek,V. Kini,H. Mashburn,S. McConnel,M. Tsao +4 more
- 01 Oct 1978
TL;DR: Three multiprocessor systems designed, implemented, and currently operational at Carnegie-Mellon University are compared and contrasted, with a special focus on reliability features.
103
Anomalous Response Times of Input Synchronizers
TL;DR: Two fundamental solutions of the metastable-state problem in the clocked systems are described and two well-known methods of reducing failure probability for SN74S74 are evaluated.
93
Anomalous Behavior of Synchronizer and Arbiter Circuits
T.J. Chaney,Charles E. Molnar +1 more
TL;DR: Observations are shown of oscillatory and metastable behavior of flip-flops in response to logically undefined input conditions such as those that occur in synchronizers and arbiters.
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