Patent
Substrate bonding with diffusion barrier structures
Daniel C. Edelstein,Douglas C. La Tulipe,Wei Lin,Deepika Priyadarshini,Spyridon Skordas,Tuan A. Vo,Kevin R. Winstel +6 more
- 30 May 2013
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TL;DR: In this paper, a metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and surfaces of a dielectric material layer embedding the copper-base metal pads in each of two substrates to be subsequently bonded.
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Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.
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Citations
Patent
Hybrid bonding with through substrate via (tsv)
Jing-Cheng Lin
- 16 Jul 2013
TL;DR: In this paper, the semiconductor device structure includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect is electrically connected to the metallization structure via the TSV.
67
Patent
Conductive barrier direct hybrid bonding
Paul M. Enquist
- 25 Aug 2015
TL;DR: In this paper, a method for forming a direct hybrid bond between a device and a device resulting from a direct-hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier.
34
Patent
Semiconductor device and method for manufacturing same
Higuchi Yuichi,Arai Hideyuki +1 more
- 03 Jan 2014
TL;DR: In this article, a space region is formed at a part of a junction interface between the first laminated body and the second laminate body by directly bonding the first junction electrode and second junction electrode with the two junction electrodes facing each other.
26
Patent
Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
Jing-Cheng Lin
- 16 Jul 2013
TL;DR: In this article, the semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconducting wafer, and a backside of a second semiconductive wafer is bonded to the front side of a first wafer.
25
Patent
Seal ring structures and methods of forming same
Kuo-Ming Wu,Kuan-Liang Liu,Wang Wen-De,Lin Yung-Lung +3 more
- 01 Aug 2017
TL;DR: In this article, a seal ring structure is proposed to separate the first IC die from the second IC die and perimetrically surround a gas reservoir between the first and second IC dies.
18
References
Patent
Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
Scot A. Kellar,Sarah Kim,R. List +2 more
- 06 Feb 2002
TL;DR: In this paper, a 3D integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer containing one or multiple IC devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines.
183
Patent
Interlocking conductor method for bonding wafers to produce stacked integrated circuits
Robert Patti
- 11 Apr 2002
TL;DR: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit are used to provide vertical connections and to bond the wafers together in this paper.
165
Patent
Three-Dimensional Integrated Circuits with Protection Layers
Chen-Hua Yu,Wen-Chih Chiou,Weng-Jin Wu,Hung-Jung Tu,Ku-Feng Yang +4 more
- 19 Dec 2006
TL;DR: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface as discussed by the authors.
61
Patent
Self-aligned barrier and capping layers for interconnects
Roy G. Gordon,Harish B. Bhandari,Yeung Au,Youbo Lin +3 more
- 20 Oct 2010
TL;DR: In this paper, an interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided, as well as methods for catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor.
53
Patent
Hybrid bonding mechanisms for semiconductor wafers
Liu Ping Yin,Szu-Ying Chen,Chen-Jong Wang,Huang Chih Hui,Xin-Hua Huang,Chao Lan Lin,Tu Yeur Luen,Chia-Shiung Tsai,Xiaomeng Chen +8 more
- 20 Aug 2015
TL;DR: In this paper, the authors proposed a method of forming a hybrid bonding structure by depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stopslayer contacts the conductive structures.
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