Structure for an asynchronous data interface

TL;DR: In this article, a multi-processor array is described that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller.

TL;DR: In this paper, the first first-in-first-out (FIFO) memory is used to connect a master, a slave, and an asynchronous interface having a FIFO memory connected to the master and the slave.

TL;DR: In this paper, a queue can receive, from a first clock domain, a first command to store data in the queue, and the queue can store the data at a first location indicated by a first pointer.

TL;DR: In this paper, the first first-in-first-out (FIFO) memory is used to connect a master, a slave, and an asynchronous interface having a FIFO memory connected to the master and the slave.

TL;DR: In this article, techniques for performing real-time backup of data in the presence of a pending hazard, such as a natural disaster, or the like, are disclosed, and a representative embodiment according to the present invention, update of the primary data is temporarily suspended after the recognition of a probable occurrence of a hazardous event.

TL;DR: In this article, a system for transferring data into and out of a first-in-first-out (FIFO) data buffer is described, which consists of a comparator circuit, multiple counter blocks, and multiple flag registers.

TL;DR: In this article, the authors present a method for managing a queue in host memory for use with a peripheral device, where the host makes a determination of the availability of space in the queue for writing new entries, in dependence upon historical knowledge of the number of queue entries that the host has authorized the device to write, and the amount of entries consumed.

TL;DR: In this paper, the authors present a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domains, where the synchronizer circuit synchronizes a first domain write request signal to the second clock signal.