Patent
Stackable semiconductor package and manufacturing method thereof
Chia-Ching Chen,Yi-Chuan Ding +1 more
- 25 Feb 2013
35
TL;DR: In this paper, the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.
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Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.
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Citations
Patent
Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
Yaojian Lin,XuSheng Bao,Kang Chen,Jianmin Fang +3 more
- 15 Mar 2013
TL;DR: In this article, a semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the die and a conductive layer is formed over the first insulating layer.
302
Patent
Fan-out semiconductor package
Jin Young Kim,Doo Hyun Park,SeungJae Lee +2 more
- 12 Jan 2017
TL;DR: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface as mentioned in this paper, and a stiffener is disposed on the third surface.
202
Patent
Semiconductor package and method of forming the same
Sang-Uk Kim,Hyo-Chang Ryu,Jin-woo Park,Dae-young Choi,Mi-Yeon Kim +4 more
- 07 Oct 2010
TL;DR: In this paper, a stress reliever disposed on a part (more specifically, a weak part) of a semiconductor chip is used to relieve thermal and/or physical stresses caused by a molding layer.
126
Patent
Semiconductor Device Packages with Fan-Out and with Connecting Elements for Stacking and Manufacturing Methods Thereof
Yi-Chuan Ding,Chia-Ching Chen +1 more
- 02 Apr 2010
TL;DR: In this paper, an embodiment of a semiconductor device package includes an interconnection unit including a patterned conductive layer, an electrical interconnect extending substantially vertically from the conductive layers, and a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package.
106
Patent
Wafer-Level Semiconductor Device Packages with Electromagnetic Interference Shielding
Chi-Tsung Chiu,Kuo-Hsien Liao,Wei-Chi Yih,Yui-Chi Chen,Chen-Chuan Fan +4 more
- 19 Nov 2009
TL;DR: In this article, the authors describe wafer-level semiconductor device packages with EMI shielding and related methods, including a grounding element that includes a connection surface electrically exposed adjacent to at least one lateral surface of the set of redistribution layers.
99
References
Patent
Method for fabricating an integrated circuit module
Raymond Albert Fillion,Robert John Wojnarowski,Michael Gdula,Herbert Stanley Cole,Eric Joseph Wildi,Wolfgang Daum +5 more
- 09 Jul 1993
TL;DR: In this article, a dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips.
560
Patent
Three-dimensional multi-chip pad array carrier
Paul T. Lin
- 02 Mar 1992
TL;DR: In this paper, a stackable three-dimensional multi-chip module (MCM) is provided whereby each level of chip carrier is interconnected to another level through reflowing of solder balls pre-bumped onto each carrier.
486
Patent
Component built-in module and method for producing the same
Seiichi Nakatani,Yasuhiro Sugaya,Toshiyuki Asahi,Shingo Komatsu +3 more
- 10 May 2005
TL;DR: In this paper, a thermal conductive component built-in module consisting of a core layer formed of an electric insulating material and a plurality of wiring patterns is presented. But the core layer has a different configuration from the outer layer.
436
Patent
Fabrication process of semiconductor package and semiconductor package
Naoki Fukutomi,Yoshiaki Tsubomatsu,Fumio Inoue,Toshio Yamazaki,Hirohito Ohhata,Shinsuke Hagiwara,Noriyuki Taguchi,Hiroshi Nomura +7 more
- 17 Mar 1995
TL;DR: In this paper, a semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors, and a nickel layer is plated on an electroplated copper foil to form a wiring pattern.
428
Patent
Single chip modules, repairable multichip modules, and methods of fabrication thereof
Charles William Eichelberger
- 20 May 1996
TL;DR: In this paper, the multichip and single chip modules are presented as well as a chips first fabrication of such modules, where a photo-patternable dielectric is disposed directly on the upper surfaces of the chips.
422