Proceedings Article10.1109/ICNC.2013.6817969
Spiking neural network based ASIC for character recognition
Shruti R. Kulkarni,Maryam Shojaei Baghini +1 more
- 23 Jul 2013
- pp 194-199
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TL;DR: The robustness of SNN is demonstrated in this work by its ability to classify the 30 out of 32 noisy characters images presented as compared to the nearest neighbour algorithm, which correctly classified only 20 of them.
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Abstract: Spiking neural networks are the recent models of artificial neural networks. These networks use biologically similar neuron models as their basic computation units. This paper presents and compares a custom spiking neural network (SNN) with a conventional nearest neighbour classifier for hand written character recognition. The classifiers are designed and simulated in 90nm CMOS technology. The two algorithms are compared in terms of their success rates and their hardware requirements (based on the area and power estimates). The classification performance of the SNN is also compared with that of second generation feedforward neural network, with the same set of images. The robustness of SNN is demonstrated in this work by its ability to classify the 30 out of 32 noisy characters images presented as compared to the nearest neighbour algorithm, which correctly classified only 20 of them. The feedforward neural network using backpropagation algorithm was able to correctly identify 29 out of 32 noisy images in MATLAB. In terms of hardware, the ASIC realizing the nearest neighbour classifier dissipates power of 1.2mW and an area of 380μm × 380μm, while the SNN dissipates 16.7mW power and an area of 1mm × 1mm. The higher area and power requirements for the SNN stem from its inherent parallel architecture. Earlier works have focused on realization of a single spiking neuron and its variants while this work brings about the application using networks of these neurons and their suitability for custom realization.
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Citations
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ASIC Implementation for Improved Character Recognition and Classification using SNN Model
S. Chaturvedi,A.A. Kurshid +1 more
TL;DR: Here, the technique of using ASIC for large scale simulations of the Izhikevich model and use RTL Clock gating approach for reducing the dynamic power and power consumption is adapted.
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A GCM neural network using cubic logistic map for information processing
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- 01 Jan 2012
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