Special Section on Terascale Computing

TL;DR: The AXIOM platform is built with the possibility of executing an application not only on a single board but also, in a distributed fashion, on multiple boards, and good scalability and a speed-up compared to other programming models such as Cilk and OpenMPI.

TL;DR: Well-known programming models that are used to exploit the Thread-Level Parallelism such as Cilk, OpenMPI and Jump are compared with DF-thread execution and obtained results show that a DF-Thread execution on a cluster of eight 4-core boards can provide a speed-up of more than 14x compared to the same configuration when using Open MPI and more than 80x when compared with a single core, single node execution.

TL;DR: The proposed design aims at combining the performance of a fine-grained data-flow architecture with the flexibility of reconfiguration, without requiring a partial reconfigurations or new bit-stream for reprogramming it.

TL;DR: In this paper, different options for simulating a 1000 general-purpose-core system are explored and the setup that successfully allowed them to evaluate their 1000 core target while running a full-system Linux operating system.

TL;DR: A hardware/software approach to fault detection that enables a system-level Fault Awareness by implementing a hierarchical Mutual Watchdog that relies on an improved high performance Network Interface Card (NIC), implementing an n -dimensional mesh topology and a Service Network.

TL;DR: Simulation shows that the proposed resource discovery model can be applied to arbitrary scales of dynamicity, both in terms of complexity and of scale, positioning this proposal as a good architecture for future many-core systems.

TL;DR: In this article, a point-to-point, low latency, 3D torus Network Controller integrated in an FPGA-based PCIe board which implements a Remote Direct Memory Access (RDMA) communication protocol is presented.

TL;DR: This paper describes the Picos Hardware Design and the latencies of the main functionality of its components, based on the synthesis of their VHDL design, and proposes Picos, an implementation of the Task Superscalar (TSS) architecture that provides hardware support to the OmpSs programming model.