Open Access
Simple Case Study in Metropolis
Haibo Zeng,Vishal Shah,Douglas Densmore,Abhijit Davare +3 more
- 01 Jan 2004
TL;DR: The case study documented in this tutorial exercises the capabilities of the Metropolis Design Environment with an industrial-sized design that consists of a functional network, an architectural network, and a mapping network.
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Abstract: The case study documented in this tutorial exercises the capabilities of the Metropolis Design Environment with an industrial-sized design. As a typical design example in Metropolis, this case study consists of a functional network, an architectural network, and a mapping network. The functional network models a simple application where data is obtained from two independent sources, manipulated in some way. This document will describe each of these three major components.
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Citations
FPGA Architecture Characterization for System Level Performance Analysis
Douglas Densmore,Adam P. Donlin,Alberto Sangiovanni-Vincentelli +2 more
- 06 Mar 2006
TL;DR: This work presents a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies and describes the characterization process for Xilinx Core Connect-based platforms and the integration of this data into the METROPOLIS modeling environment.
Automated mapping for heterogeneous multiprocessor embedded systems
Abhijit Davare
- 01 Jan 2007
TL;DR: Automated Mapping for Heterogeneous Multiprocessor Embedded Systems automates the mapping process for heterogeneous multi-modal systems and provides real-time information about the components in the system to improve the efficiency of the system.
9
A Platform-based Design Flow for Kahn Process Networks
Abhijit Davare,Qi Zhu,Alberto Sangiovanni-Vincentelli +2 more
- 01 Jan 2006
TL;DR: This work explores automated solutions to multimedia applications on multiprocessor architectures by considering two separate directions of research and developing a specialized design flow and associated algorithms to solve this problem.
9
Single and multi-cpu performance modeling for embedded systems
Alberto Sangiovanni-Vincentelli,Trevor Meyerowitz +1 more
- 01 Jan 2008
TL;DR: An approach for automatically annotating timing information obtained from a cycle-level model back to the original application source code is developed, and the annotated source code can then be simulated without the underlying architecture and still maintain good timing accuracy.
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