Silicon-based vertical MOSFETs

TL;DR: In this article, a computational analysis of the ballistic saturation velocity for low-dimensional nano-devices is presented, and the saturation velocity is found to be ballistic regardless of the device dimensions.

TL;DR: In this article, a double gate structure on each side of insulating pillar for nanodevice applications is presented, and the body doping effect on vertical channel for channel length, L g = 50nm and analyzing its effect towards such small devices is successfully performed.

TL;DR: In this paper, a design and simulation analysis of vertical MOSFET structure with double gate structure on each side of insulating pillar for nanodevice applications is presented, and the body doping effect on vertical channel for channel length, L g = 50nm and analyzing its effect towards such small devices was successfully performed.

TL;DR: In this paper, the authors present a review of the properties of Semiconductor devices and compare them with the Monte Carlo simulation of the two-dimensional electron gas (2DEG) model.

TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.

TL;DR: Realistic estimates of the conduction- and valence-band-edge energies, higher-energy-band minima, effective masses, deformation potentials, and heterostructure band offsets for the whole range of alloy compositions x and y and strain are presented.

TL;DR: In this paper, the authors show that implanted B and P dopants in Si exhibit transient enhanced diffusion (TED) during initial annealing, due to Si interstitials being emitted from the region of the implant damage.