Serial bus test device

TL;DR: In this paper, the authors propose a simple configuration to acquire all packets sent on a serial bus with simple configuration, where a physical layer circuit 4n receives a packet transmission signal from the serial bus 1 and outputs received data, a reception control circuit 31 writes sequentially the received data from data lines D0 -D7 via a register circuit 20 to a capture memory 30.

Abstract: PROBLEM TO BE SOLVED: To acquire all packets sent on a serial bus with a simple configuration. SOLUTION: When a physical layer circuit 4n receives a packet transmission signal from a serial bus 1 and outputs received data, a reception control circuit 31 writes sequentially the received data from data lines D0 -D7 via a register circuit 20 to a capture memory 30. Furthermore, when a link layer circuit 5. outputs transmission data configuring a transmission packet addressed to a node device 21 of a test object to the physical layer circuit 4n , the physical layer circuit 4n converts the data into a transmission signal and outputs it to a high speed serial bus 1, and the reception control circuit 31 writes sequentially transmission data received from the data lines D0 -D7 via the register circuit 20 in parallel with above to the capture memory 30. A controller displays contents of the capture memory 30 on a display device.