Patent
Sequence control circuit
Takahashi Yukio,Hagiwara Noboru,Tachibana Masatoshi,Yano Masaaki,Oouchi Yasunori +4 more
- 22 Nov 1979
2
TL;DR: In this paper, the authors propose to output the two addresses at the same time, by inputting the first and second data and constituting the first-and second address production circuits, and firstand second selection circuits on a LSI of one substrate.
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Abstract: PURPOSE:To enable to output the two addresses at the same time, by inputting the first and second data and constituting the first and second address production circuits first and second registers, and first and second selection circuits on a LSI of one substrate. CONSTITUTION:The address forming circuit 12 inputs data 10 and 25, modifies the input data based on the content of instruction, and outputs the address data 14. The address forming circuit 13 inputs data 11 and outputs the address data 15 different in the data 14. The data 14, 15 are parallelly produced with the same instruction and are held at the registers 16, 17 at the same time. The selection circuit 22 selects either of the output data 19, 20 in the registers 16 and 17 with the selection signal 24 to output the next address data 25, and further, outputs the other output data. The selection circuit 23 outputs the state of the other circuit 18 independently based on the selection signal 27. Thus, the sequence control circuit in large scale integration LSI 28 which can output different addresses in time sharing manner and also can output two addresses at the same time, can be established.
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Citations
Patent
Program controlling system
Ueda Katsuhiko,Suzuki Toshiaki,Takashi Sakao +2 more
- 24 Feb 1982
TL;DR: In this paper, the authors propose to improve the efficiency of the use of the whole memory by planting the first address of an instruction group that executes repetitively in the stack area of a memory for work by indicating with the stack pointer.
2
Patent
Memory address control method
Takaoka Masanao
- 16 Aug 1991
TL;DR: In this article, the addresses of a memory 24 set at the side of a lower-rank word (16 bits) and a memory 25 set at a side of higher-rank words (16 bit) are divided separately from each other and can be inputted.
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