Patent
Semiconductor memory having non-standard form factor
Thomas Vogelsang
- 26 Jan 2010
5
TL;DR: In this paper, a semiconductor memory chip including error correction circuitry is configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each coded word to form a corresponding coded word comprising the data bits of the data word and a plurality of error correction code bits.
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Abstract: A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.
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Citations
Patent
Joint encoding of logical pages in multi-page memory architecture
Ara Patapoutian,Deepak Sridhara,Bruce Douglas Buch +2 more
- 17 May 2010
TL;DR: In this article, multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells.
26
Patent
Error protection for integrated circuits
William V. Huott,Kevin W. Kark,John G. Massey,K. Paul Muller,David L. Rude,David Wolpert +5 more
- 23 Jan 2013
TL;DR: In this article, a method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the arrays in the insensitive direction.
4
Patent
Error protection for a data bus
William V. Huott,Kevin W. Kark,John G. Massey,K. Paul Muller,David L. Rude,David Wolpert +5 more
- 15 Jan 2013
TL;DR: In this article, a system for error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or multiple buses, each array disposed on one of the buses.
4
Patent
Placement of storage cells on an integrated circuit
William V. Huott,Kevin W. Kark,John G. Massey,K. Paul Muller,David L. Rude,David Wolpert +5 more
- 15 Jan 2013
TL;DR: In this article, a method for configuring the placement of a plurality of storage cells on an integrated circuit is presented, where each of the storage cells is protected by an error control mechanism and the minimum distance between any two storage cells belonging to one of the plurality of words is greater than a minimum distance.
4
Patent
Shared error protection for register banks
William V. Huott,Kevin W. Kark,John G. Massey,K. Paul Muller,David L. Rude,David Wolpert +5 more
- 15 Jan 2013
TL;DR: In this paper, a method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of registers into an array, and then adding a product code to the array, the product code including applying the second error control mechanism to the first error control mechanisms.
References
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Patent
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Sompong P. Olarig
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41
Patent
Memory configuration with a central connection area
Brox Martin,Karl-Peter Pfefferl,Helmut Schneider,Robert Kaiser,Dominique Savignac +4 more
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TL;DR: A memory configuration includes a central connection area surrounded annularly by cell arrays having memory cells as mentioned in this paper, which is suitable for a side ratio of 2:1 all the peripheral circuits are preferably disposed in the center connection area.
32
Patent
Semiconductor memory device with error correcting circuit
Yoshihiro Takemae
- 17 Mar 1987
TL;DR: In this paper, the authors propose a data path between the access control circuit and the plurality of cell blocks, so that the data which is input from and output to the access controller can be converted to a predetermined bit converted data (so called code) by the ECC circuit.
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