Semiconductor memory element

TL;DR: In this article, a semiconductor memory circuit is described for use in a memory array which is capable of permitting data contained in an entire column or in a entire row to be accessed simultaneously.

TL;DR: In this article, the authors proposed to restrain the time margin between the select operation and the driving operation to the required minimum to improve the operation speed by controlling applying of driving clocks through a false select unit circuit equivalent to a select unit.

TL;DR: In this paper, a gate circuit for control of a word address decoder which contains a pair of memory cells and can read and write the same contents at a time is presented, where a writing action is carried out with a high potential applied to a control terminal T, two of word selection lines WT1, WT2 set in pairs have high potentials by the combinations of high and low levels of the signals applied to terminals A1-Ai excluding a terminal A0.

TL;DR: In this paper, the authors propose to separate the writing and reading of data and to prevent the delay of a reading speed by executing error detection and correction by removing a determined sense amplifier output without passing a usual Y decoder.