Patent
Semiconductor memory device
Ueki Makoto,Masuzaki Koji,Matsudaira Masaharu,Hase Takashi,Hayashi Yoshihiro +4 more
- 21 Jul 2005
651
TL;DR: In this article, a mixing layer is constituted that Ru is diffused in an LaNiO 3 -based film in order to raise adhesiveness of an Ru-based layer to the interface of the LaNiOs 3-based film, using lower electrodes wherein perovskite type conductivity oxide La NiO 3 and Ru which is noble metal are laminated, and moreover the orientation degree of Ru (002) is 90% or more.
read more
Abstract: PROBLEM TO BE SOLVED: To enable mixed mounting with a highly efficient electrical body capacitative element and a highly efficient logic circuit, by forming a dielectrics capacitative element of perovskite structure at low temperature, as well as by suppressing characteristic fluctuation and characteristics degradation of an integrated circuit. SOLUTION: In Pb-based perovskite dielectrics capacitative element, a mixing layer is so constituted that Ru is diffused in an LaNiO 3 -based film in order to raise adhesiveness of an Ru-based layer to the interface of the LaNiO 3 -based film, using lower electrodes wherein perovskite type conductivity oxide LaNiO 3 and Ru which is noble metal are laminated, and moreover the orientation degree of Ru (002) is 90% or more, and LaNiO 3 has a preference orientation degree (100), so that the orientation and grain size of a PZT film are controlled. Thus, the PZT film excellent in flatness and orientation is obtained. COPYRIGHT: (C)2005,JPO&NCIPI
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Semiconductor device, and manufacturing method thereof
Kengo Akimoto,Tatsuya Honda,Norihito Sone +2 more
- 01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
1.5K
Patent
Powered tacker instrument
Ernest Aranyi,Gregg Krehel,Thomas Wenchell,Earl M. Zergiebel +3 more
- 09 May 2008
TL;DR: In this article, the authors used a self-contained power assembly to rotate the surgical fasteners into tissue, which allowed for rotation, as well as distal longitudinal movement, relative to the powered tacker device.
803
Patent
Three dimensional semiconductor memory devices and methods of fabricating the same
Kwang Soo Seol,Chanjin Park,Ki-Hyun Hwang,Han-mei Choi,Sunghoi Hur,Wan Sik Hwang,Toshiro Nakanishi,Kwangmin Park,Juyul Lee +8 more
- 12 Mar 2013
TL;DR: In this article, the three-dimensional semiconductor memory devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor pattern and the electrode structures.
526
Patent
Cut-mask patterning process for fin-like field effect transistor (FinFET) device
Ho Wei De,Kuei-Liang Lu,Ming-Feng Shieh,Ching-Yu Chang +3 more
- 09 Feb 2012
TL;DR: In this article, a method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, is presented, where a first layer is formed above the surface and above the plurality of elongated features, and patterned with an end cutting mask.
412
Patent
Nonvolatile Semiconductor Memory Device
Noboru Shibata,Tomoharu Tanaka +1 more
- 09 Mar 2007
TL;DR: In this paper, a memory cell array has a first and a second storage area, the first storage area has a memory elements selected by an address signal, and the second storage is a control circuit with a fuse element.
385
References
Patent
Dielectric element and manufacturing method therefor
Toshihide Nabatame,Takaaki Suzuki,Kazutoshi Higashiyama,Oishi Tomoji +3 more
- 10 Nov 1997
TL;DR: In this article, a thin ferroelectric element which has high Pr, low Ec, and excellent pressure resistance is provided by using a ferro electrode layer containing insulating particles, which can restrain the leakage current generated through the grain boundary of a crystal.
37
Patent
Semiconductor device and manufacturing method therefor
Okura Seiji,Oda Koji,Sawada Masato +2 more
- 22 Feb 2002
TL;DR: In this article, a multilayer wiring, constituted of a first metal wiring and a second metal wiring, is formed on a semiconductor substrate, and a fluorinated silicate glass film 3 as the inter-metal insulating film is formed between the metal wires.
25
Effect of Sputtering-Target Composition on the Texturization of LaNiO3 Thin Films on Si Substrate
TL;DR: In this paper, the authors used X-ray diffraction (XRD) and Xray absorption spectroscopy (XAS) to characterize the texturization of LaNiO3 thin films with targets of various compositions and at different substrate temperatures.
6
Patent
Semiconductor device having capacitor
Kuroiwa Takeharu
- 24 Nov 1998
TL;DR: In this article, a storage node is formed on an interlayer insulating layer 27, so as to be in contact with source/drain regions 15 of a MOS transistor passing through a plug layer 9.
5