Patent
Semiconductor integrated circuit device
Hoshi Yasuhiko
- 22 Jun 1990
33
TL;DR: In this article, the authors proposed to reduce the generation of overshoot or undershoot and attain high speed output signal by inserting a resistor between a source of an input element and a power supply line, and providing a switch element in parallel with a resistor.
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Abstract: PURPOSE:To reduce the generation of overshoot or undershoot and to attain high speed output signal by inserting a resistor between a source of an input element and a power supply line, and providing a switch element in parallel with a resistor. CONSTITUTION:A resistor R1 is inserted between a source of a P-channel output MOSFET Q1 and a power supply line Vcc, a resistor R2 is inserted between a source of an N-channel output MOSFET Q3 and a ground line and a P- channel MOSFET Q2 and an N-channel MOSFET Q4 are provided respectively in parallel with the resistors R1, R2. Then the FETs Q2, Q4 are subject to complementary switch control with an output MOSFET Q1 or Q3 with a proper delay time with respect to an input signal Di by an output signal Do. The switch MOSFETs Q2, Q4 are changed from the on-state into the off-state when the output signal in close to the ground level or power level and a resistor is inserted in series with the output MOSFET to reduce undershoot or overshoot and to attain high speed output signal.
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Citations
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Semiconductor integrated circuit device having power reduction mechanism
Masashi Horiguchi,Kunio Uchiyama,Kiyoo Itoh,Takeshi Sakata,Masakazu Aoki,Takayuki Kawahara +5 more
- 30 Oct 2002
TL;DR: In this paper, the authors describe a logic gate with at least two MOS transistors connected to a first potential point and a second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the gate.
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Kerry D. Maletsky,James Peter Ward,Michael J. Steinmetz,Daryl Carvis Cromer,Gregory B. Pruett +4 more
- 14 Nov 1997
TL;DR: In this paper, a memory array is divided into memory blocks, each block having a corresponding access control bit, and at least one such block is further subdivided into pages, each page having corresponding control bit.
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System for programming EEPROM with data loaded in ROM by sending switch signal to isolate EEPROM from host system
James R. Robb,David S. Silver +1 more
- 07 Mar 1991
TL;DR: An EEPROM programming circuit is described in this article, which provides on-boardrogramming of a EEPRAM memory using: a microprocessor, a bootstrap ROM, a UART communications port, and a flip flop switch system.
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Tomita Kazuhiro,Isoda Masahito,Horibe Yasushi +2 more
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TL;DR: In this article, an ESD protective element has a structure wherein the spread of a depletion layer is formed so as to be close to an emitter region when the part between a collector and a base is reversebiased and it is constituted in such a way that it is broken down more easily than other circuit elements.
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Semiconductor device having an isolating portion between two circuit regions
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TL;DR: In this paper, a P type well region is formed on the semiconductor substrate and between the digital circuit region and the analog circuit region, and an N type first diffusion layer is formed in the well region.
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