Patent
Semiconductor device, semiconductor module, electronic equipment, method for manufacturing semiconductor device, and method for manufacturing semiconductor module
Koji Yamaguchi
- 09 Jan 2004
58
TL;DR: In this paper, Grooves 4 a - 4 c are provided at positions of scribe lines SL of semiconductor substrates 1 a - 1 c ; and conductive material 11 is filled in the grooves provided in sections of the semiconductor substrate.
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Abstract: To suppress enlargement of the chip size, and improve the reliability in interlayer connections. Grooves 4 a - 4 c are provided at positions of scribe lines SL of semiconductor substrates 1 a - 1 c ; and conductive material 11 is filled in the grooves 4 a - 4 c provided in sections of the semiconductor substrates 1 a - 1 c after the semiconductor substrates 1 a - 1 c are stacked in layers.
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Citations
Patent
Chip package and fabrication method thereof
Chia-Lun Tsai,Tsang-Yu Liu,Chia-Ming Cheng +2 more
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TL;DR: In this paper, a chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate, where a signal and an EMI ground pad are disposed on the pad region.
225
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157
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Reza A. Pagaila,Byung Tai Do,Linda Pei Ee Chua +2 more
- 06 May 2010
TL;DR: In this article, a gap is made between the semiconductor die and a portion of the insulating material is removed to form a first through hole via (THV), a conductive lining is conformally deposited in the first THV.
91
Patent
Display apparatus and manufacturing method thereof
Yeun Tae Kim,Hyang-Shik Kong,Nam-Seok Roh,Hong-Sick Park,Chang-Oh Jeong,Jinho Ju,Byeong-Jin Lee,Chae Kyungtae,Jiseong Yang +8 more
- 22 Feb 2013
TL;DR: In this paper, a display apparatus includes a base substrate, a pixel on the base substrate and a color filter part between the pixel and the pixel, including a cover layer defining a TSC (Tunnel Shaped Cavity), an image display part provided in the TSC, and first and second electrodes which apply an electric field to the image display.
84
Patent
Semiconductor device and manufacturing method for the same
Kengo Akimoto,Junichiro Sakata,Shunpei Yamazaki +2 more
- 19 Jul 2012
TL;DR: In this article, a method for manufacturing a highly reliable semiconductor device including thin film transistors which have stable electric characteristics and are formed using an oxide semiconductor was proposed, which includes the steps of: forming a first conductive film including at least one of titanium, molybdenum, and tungsten, over the oxide semiconductors, forming a second conductive material including a metal having lower electronegativity than hydrogen over the first, and forming a source electrode and a drain electrode by etching of the first and second conductivities.
53
References
Patent
Three dimensional integrated circuit package
John K. Woodman
- 18 Sep 1989
TL;DR: In this article, a three-dimensional high density package for integrated circuits for which integrated circuits are placed onto substrate layers and then stacked together is described, and techniques for interconnecting the layers to one another and for connecting the layer to external circuitry are also disclosed.
418
Patent
Integrated circuit chip stacking
Floyd Eide
- 04 Nov 1988
TL;DR: In this article, a plurality of integrated circuits are packaged within chip carriers and stacked, on one top of the other, on a printed circuit board, each of the input/output data terminals, power and ground terminals of the chips are connected in parallel.
240
Patent
Double cavity semiconductor chip carrier
John Francis Gogal
- 08 Apr 1981
TL;DR: In this paper, a double cavity semiconductor chip carrier (100) is described, which comprises a multilayer ceramic sandwich structure having a pair of semiconductor receiving cavities in the opposite faces thereof.
207
Patent
Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation
Barry K. Gilbert,Daniel J. Schwab +1 more
- 05 Oct 1982
TL;DR: In this article, a carrier apparatus for mounting logic components on the surface of a circuit board is described, which utilizes ground and voltage planes together with alternating signal (118) and AC ground (121) traces.
187
Patent
Stacked silicon die carrier assembly
Hamid Shokrgozar,Leonard W. Reeves,Bjarne Heggli +2 more
- 26 Jul 1994
TL;DR: In this article, a stacked die carrier assembly and method for packaging and interconnecting silicon chips such as memory chips is described, where the chip is wire bonded to the conductor pattern on the substrate and each conductor is routed to the edge of the substrate where it is connected to a half-circle of a metalized through hole.
176
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