Patent
Self-forming embedded diffusion barriers
Cyril Cabral,Daniel C. Edelstein,Juntao Li,Takeshi Nogami +3 more
- 04 Aug 2015
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TL;DR: In this article, an M x level, M x+1 level, and a seed alloy region adjacent to the M x + 1 metal separating the m x metal from the M X+1 metal are discussed.
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Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an M x level including an M x metal in an M x dielectric, an M x+1 level above the M x level including an M x+1 metal in an M x+1 dielectric, an embedded diffusion barrier adjacent to the M x+1 dielectric; and a seed alloy region adjacent to the M x+1 metal separating the M x metal from the M x+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.
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Citations
Patent
Cobalt top layer advanced metallization for interconnects
Daniel C. Edelstein,Chih-Chao Yang +1 more
- 23 Jan 2017
TL;DR: In this article, a pattern is provided in a dielectric layer in which a set of features are patterned for metal conductor structures, and an adhesion promoting layer is created disposed over the patterned dielectrics.
7
Patent
Metal oxysilicate diffusion barriers for damascene metallization with low rc delays and methods for forming the same
Ganesh Hegde,Mark S. Rodder,Rwik Sengupta,Chris Bowen +3 more
- 22 Oct 2015
TL;DR: In this paper, a method to form a metal-oxysilicate diffusion barrier for damascene metallization is described, where a trench is formed in an Inter Layer Dielectric (ILD) material.
6
Patent
IC structure with interface liner and methods of forming same
Xunyuan Zhang,Moosung M. Chae +1 more
- 01 Feb 2018
TL;DR: In this article, the authors proposed a method of forming an integrated circuit (IC) structure, which includes: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, overlaying the metal layer including a first metal doped with a second metal.
6
Patent
Semiconductor device structure and method for forming the same
Rueijer Lin,Chen-Yuan Kao,Chun-Chieh Lin,Huang-Yi Huang +3 more
- 02 Oct 2014
TL;DR: In this article, a gate stack, a spacer layer, and a dielectric layer over a substrate is constructed, followed by a conductive contact structure in the through hole.
5
Patent
Integrated circuit devices and methods
Jeffrey Junhao Xu,Junjing Bao,John Jianhong Zhu,Stanley Seungchul Song,Niladri Narayan Mojumder,Choh fei Yeap +5 more
- 05 Aug 2015
TL;DR: An integrated circuit device includes a first metal layer including aluminum as mentioned in this paper, and an interconnect structure includes a layer of first material including aluminum, and a self-forming barrier layer that includes aluminum.
5
References
Patent
Semiconductor device and method of manufacturing the same
Hashimoto Yoshihito,Hashimoto Yoichi +1 more
- 06 Sep 2012
TL;DR: In this article, a flexible optical waveguide substrate is used to connect an LSI chip to an optical element chip through the package substrate, and the other end of the flexible waveguide is optically coupled to the optical element.
47
Patent
Dopant Enhanced Interconnect
Rohan Akolkar,Sridhar Balakrishnan,Adrien R. Lavoie,Tejaswi K. Indukuri,James S. Clarke +4 more
- 12 Feb 2010
TL;DR: In this article, an interconnect structure that is resistance to electromigration is described, where a lintern is deployed underneath a seed layer of the structure, and a dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer.
35
Patent
Method of manufacturing semiconductor apparatus, and semiconductor apparatus
Hisaya Sakai,Noriyoshi Shimizu +1 more
- 30 Jan 2008
TL;DR: In this article, a method of manufacturing a semiconductor apparatus which includes the steps of forming a via hole and a wire trench reaching an underlying wire in an interlayer insulation film formed on the underlying wire is described.
35
Patent
Semiconductor device, its manufacturing method, and sputtering target material for use in the method
Junichi Koike
- 27 Feb 2007
TL;DR: In this paper, a semiconductor device is provided on an insulating film with a wiring, which includes the wires, a wiring main body, and a barrier layer made of an oxide containing Cu and Si and Mn.
31
Patent
Film forming method and processing system
Kenji Matsumoto,Yasushi Mizusawa +1 more
- 24 Jun 2011
TL;DR: In this paper, a transition metal-containing film processing method was proposed for metal film forming on a surface of a target substrate to be processed in an evacuable processing chamber, a recessed portion being formed on the surface of the target substrate.
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