Patent
Security in virtualized computer programs
Joseph Epstein
- 03 Oct 2012
57
TL;DR: In this paper, the authors propose a data processing method to intercept page faults associated with writing pages of memory that contain a computer program, including page faults resulting from a guest domain attempting to write a memory page that is marked as not executable.
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Abstract: In an embodiment, a data processing method comprises implementing a memory event interface to a hypercall interface of a hypervisor or virtual machine operating system to intercept page faults associated with writing pages of memory that contain a computer program; receiving a page fault resulting from a guest domain attempting to write a memory page that is marked as not executable in a memory page permissions system; determining a first set of memory page permissions for the memory page that are maintained by the hypervisor or virtual machine operating system; determining a second set of memory page permissions for the memory page that are maintained independent of the hypervisor or virtual machine operating system; determining a particular memory page permission for the memory page based on the first set and the second set; processing the page fault based on the particular memory page permission, including performing at least one security function associated with regulating access of the guest domain to the memory page.
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Citations
Patent
Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
Ruchira Sasanka,Abhinav Das,Jeffrey J. Cook,Jayaram Bobba,Arvind Krishnaswamy,David I. Sager,Suresh Srinivas +6 more
- 26 Jun 2012
TL;DR: In this paper, a hardware and software system to automatically decompose a program into multiple parallel threads is described, where the analysis includes identifying dependencies within the single-threaded region, determining portions of the single threaded region of executing program code which may be executed in parallel based on the analysis, assigning the portions to two or more parallel execution tracks and executing the portions in parallel across the assigned execution tracks.
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Patent
Instruction and logic to perform dynamic binary translation
Abhay S. Kanhere,Paul Caprioli,Koichi Yamada,Suriya Madras-Subramanian,Suresh Srinivas +4 more
- 30 Sep 2011
TL;DR: In this paper, a micro-architecture may provide a hardware and software co-designed dynamic binary translation, which is performed by using a binary translation translator to determine a hot spot region for translation and then generating the translated code using a second instruction set.
33
Patent
Systems and methods for security in computer systems
Michael Guidry
- 06 Sep 2014
TL;DR: In this paper, virtualization technology is leveraged to mask the computer system machine architecture to prevent the delivery of payloads into memory by malicious users, and the denial of payload delivery prevents the execution of malicious actions.
29
Patent
Automated protection against computer exploits
Mikhail A. Pavlyushchik
- 10 Oct 2012
TL;DR: In this paper, the authors present a memory access control arrangement in which at least write and execute privileges are enforced for allocated portions of memory An association of the process thread and the first portion of memory is recorded, and the exception type being determined as an execute exception is analyzed for a presence of malicious code.
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Patent
Service partition virtualization system and method having a secure application
Robert J. Sliwa,Brittney Burchett,Michael J. DiDomenico +2 more
- 17 Oct 2014
TL;DR: In this article, the authors present a secure application system and method for a host computing device, which includes an ultraboot application that operates in the less privileged user memory and divides the host computing devices into a resource management partition, at least one virtual service partition and at least a virtual guest partition.
18
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