SDLcheck: A Model Checking Tool
Vladimir Levin,Hüsnü Yenigün +1 more
- 18 Jul 2001
- pp 378-381
TL;DR: SDLcheck is a verification tool developed to support model checking for asynchronous (concurrent) programs written in SDL 1, 2.
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Abstract: SDLcheck is a verification tool developed to support model checking for asynchronous (concurrent) programs written in SDL 1, 2. Given an SDL program and a specification of a desired behavior of the program, SDLcheck generates a verification model that consists of two .-automata, P and T : P models the program and T the specification. Then, the automaton language containment, L(P) . L(T ), is tested by model checking with Cospan [3].
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Citations
Model checking for an executable subset of UML
Fei Xie,Vladimir Levin,James C. Browne +2 more
- 26 Nov 2001
TL;DR: An approach to model checking software system designs specified in xUML, an executable subset of UML, based on automatic translation from xU ML to S/R, the input language of the COSPAN model checker.
46
Combining Software and Hardware Verification Techniques
Robert Paul Kurshan,Vladimir Levin,Marius Minea,Doron Peled,Hüsnü Yenigün +4 more
- 01 Nov 2002
TL;DR: This paper suggests a modification of partial order reduction, allowing its combination with any BDD-based verification tool, and describes a co-verification methodology developed using these techniques jointly, suggesting that for moderate–size systems the method is ready for industrial application.
ObjectCheck: A Model Checking Tool for Executable Object-Oriented Software System Designs
Fei Xie,Vladimir Levin,James C. Browne +2 more
- 08 Apr 2002
TL;DR: ObjectCheck has facilitated effiective model checking of non-trivial software system designs represented as xUML models and ongoing research in state space reduction at the xU ML model level shows significant promise for enabling model checking.
Formal hardware specification languages for protocol compliance verification
TL;DR: This work surveys the field of candidate languages for protocol compliance verification, limiting the discussion to languages originally intended for hardware and software design and verification activities.
32
Compressing Transitions for Model Checking
Robert P. Kurshan,Vladimir Levin,Hüsnü Yenigün +2 more
- 27 Jul 2002
TL;DR: In this paper, an optimization technique is presented that compresses a chain of transitions into a single jump transition, thus making a model smaller prior to model checking, and conditions that allow such compressions to preserve next-time-free LTL.
References
The model checker SPIN
Gerard J. Holzmann
- 01 May 1997
TL;DR: An overview of the design and structure of the verifier, its theoretical foundation, and an overview of significant practical applications are given.
•Book
Computer-Aided Verification of Coordinating Processes: The Automata-Theoretic Approach
Robert P. Kurshan
- 06 Feb 1995
TL;DR: Theories of L-automaton/L-process, L-matrix, and String Acceptors are compared to Boolean Algebra, which describes the construction of language-based Algebra.
902
Static Partial Order Reduction
Robert Paul Kurshan,Vladdimir Levin,Marius Minea,Doron Peled,Doron Peled,Hüsnü Yenigün +5 more
- 28 Mar 1998
TL;DR: The process of this invention creates a modified state graph generator with appended rules that allow any desired state searching tactic to be employed when states and transitions are considered in the course of verification.
IF: an intermediate representation for SDL and its applications
Marius Bozga,Jean-Claude Fernandez,Lucian Ghirvu,Susanne Graf,Jean-Pierre Krimm,Laurent Mounier,Joseph Sifakis +6 more
- 01 Jan 1999
TL;DR: Work of a project for the improvement of a specification/validation toolbox integrating a commercial toolset ObjectGEODE and different validation tools such as the verification tool CADP and the test sequence generator TGV is presented.
Model Checking SDL with Spin
Dragan Bošnački,Dennis Dams,Leszek Holenderski,Natalia Sidorova +3 more
- 25 Mar 2000
TL;DR: An attempt to use the model checker Spin as a verification engine for SDL, with special emphasis put on the verification of timing properties of SDL models, is presented.