Scalable Coherent Interface
K. Alnaes,E.H. Kristiansen,D.B. Gustavson,D.V. James +3 more
- 27 Feb 1989
- pp 536-538
TL;DR: The Scalable Coherent Interface Project is establishing an interface standard for very-high-performance multiprocessors, supporting a cache-coherent-memory model scalable to systems with up to 64K nodes, and will supply a peak bandwidth per node of 1 Gb/s.
read more
Abstract: The scalable coherent interface (SCI) project (formerly known as SuperBus) is based on experience gained during the development of Fastbus (IEEE 960), Futurebus (IEEE 896.1) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 Gb/s per processor; efficient support of a coherent distributed-cache image of shared memory; and support for segmentation, bus repeaters, and general switched interconnections like Banyon, Omega, or full crossbars. SCI abandons the immediate handshake characteristics of the present generation of buses in favor of a packet-based protocol. SCI avoids wire-ORs, broadcasts, and even ordinary passive bus structures, except that a lower-performance (1 Gb/s per backplane instead of per processor) implementation using a register insertion ring architecture on a passive backplane appears to be possible using the same interface as for the more costly switch networks. A summary is presented of current directions, and the status of the work in progress is reported. >
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Figures
Citations
In-Memory Big Data Management and Processing: A Survey
TL;DR: This survey aims to provide a thorough review of a wide range of in-memory data management and processing proposals and systems, including both data storage systems and data processing frameworks.
Patent
Protocol for communication with dynamic memory
Richard M. Barth,Frederick Abbot Ware,John B. Dillon,Donald C. Stark,Craig E. Hampel,Matthew Murdy Griffin +5 more
- 18 Oct 1996
TL;DR: In this paper, a system and method for performing data transfers within a computer system is presented, which includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed.
210
Patent
Memory system topologies including a buffer device and an integrated circuit memory device
Ian Shaeffer,Ely K. Tsern,Craig E. Hampel +2 more
- 10 Feb 2010
TL;DR: In this paper, an integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices using a single fly-by (or bus) signal path.
174
Patent
Configurable width buffered module having a bypass circuit
Richard E. Perego,Fred Ware,Ely K. Tsern,Craig E. Hampel +3 more
- 18 May 2004
TL;DR: In this paper, a configurable width buffer device is coupled to at least one memory device (by way of an internal channel), entry pin and exit pin on the memory module.
137
Patent
Configurable width buffered module having switch elements
Fred Ware,Richard E. Perego,Ely K. Tsern +2 more
- 13 Jul 2004
TL;DR: In this paper, an asymmetric switch topology is proposed for increasing the number of memory modules to more than two memory modules without adding switch elements serially on each channel, while also achieving many of the benefits associated with point-to-point topology.
125
References
Scalable I/O architecture for buses
D.V. James
- 27 Feb 1989
TL;DR: The author discusses current IEEE activities on the P1394 bus standard and the P1596 interconnect, which concern the definition of standard control register locations, formats, and functions, and several of the scalable features of the I/O architecture are described.
39
IEEE P1596, a scalable coherent interface for gigabyte/sec multiprocessor applications
D.B. Gustavson
- 01 Feb 1989
TL;DR: Scalable coherent interface goals include a minimum bandwidth of 1 Gb/s per processor; efficient support of a coherent distributed-cache image of shared memory; and support for segmentation, bus repeaters, and general switched interconnections like Banyan, Omega, or full crossbar networks.
The Scalable Coherent Interface, IEEE P 1596, status and possible applications to data acquisition and physics
TL;DR: The Scalable Coherent Interface (SCI) goals include a minimum bandwidth of 1 GB/s per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks.
An evaluation of directory schemes for cache coherence
Anant Agarwal,Richard Simoni,John L. Hennessy,Mark Horowitz +3 more
- 17 May 1988
TL;DR: In this article, the cache coherence in shared-memory multiprocessors has been addressed using two basic approaches: directory schemes and snoopy cache schemes, which have been given less attention in the past several years.