Proceedings Article10.1109/ICCAD.1991.185188
RITUAL: a performance driven placement algorithm for small cell ICs
Arvind Srinivasan,Kamal Chaudhary,Ernest S. Kuh +2 more
- 11 Nov 1991
- pp 48-51
118
TL;DR: An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described and yields very good results, as is shown on a set of real examples.
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Abstract: An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described. Using sophisticated mathematical techniques, one is able to solve large problems quickly and effectively. The algorithm is very simple and elegant, making it easy to implement. In addition, it yields very good results, as is shown on a set of real examples. The algorithm was tested on the ISCAS set of logic benchmark examples using parameters for 1 mu m CMOS technology. On average , there is a 25% improvement in the wire delay for these examples compared to TimberWolf-5.6 with a small impact on the chip area. >
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Citations
Efficient and effective placement for very large circuits
Wern-Jieh Sun,Carl Sechen +1 more
- 07 Nov 1993
TL;DR: A new hierarchical annealing-based placement program which yields total wire length reductions of up to 9% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0.
202
Timing Driven Placement for Large Standard Cell Circuits
William Swartz,Carl Sechen +1 more
- 01 Jan 1995
TL;DR: The timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells.
Interconnect design for deep submicron ICs
Jason Cong,Zhigang Pan,Lei He,Cheng-Kok Koh,Kei-Yong Khoo +4 more
- 13 Nov 1997
TL;DR: A unified approach that considers topology optimization, wiresizing optimization, and waveform optimization simultaneously, and is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot, and routing cost.
A novel net weighting algorithm for timing-driven placement
Tim Kong
- 10 Nov 2002
TL;DR: This paper presents a novel net weighting algorithm based on the concept of path-counting, and applies it in timing-driven FPGA placement application, and theoretically this is the first ever known accurate, all-path counting algorithm.
121
References
Performance-Driven Placement of Cell Based IC's
M.A.B. Jackson,Ernest S. Kuh +1 more
- 01 Jun 1989
TL;DR: A novel approach to performance-driven placement is presented, combining timing analysis and physical design to dynamically optimize the performance of the chip during placement.
182
Improved simulated annealing algorihm for row-based placement.
Carl Sechen,Kai Win Lee +1 more
- 01 Dec 1987
113
RITUAL: a performance driven placement algorithm
TL;DR: An algorithm for obtaining a placement of large scale cell-based ICs subject to performance constraints, formulated as a constrained programming problem and solved in two phases: continuous and discrete.
80
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