Journal Article10.1109/82.204130
RITUAL: a performance driven placement algorithm
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TL;DR: An algorithm for obtaining a placement of large scale cell-based ICs subject to performance constraints, formulated as a constrained programming problem and solved in two phases: continuous and discrete.
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Abstract: An algorithm for obtaining a placement of large scale cell-based ICs subject to performance constraints is described. The problem is formulated as a constrained programming problem and is solved in two phases: continuous and discrete. Constraints are placed on total path delays including cell and interconnect delays, and the behavior of all the paths is captured. Mathematical techniques and heuristics based on Lagrangian relaxation are used to find an approximate solution to the constrained problem. The algorithm yields good results, as shown on a set of real examples. On the average, between 8% and 30% improvement in the interconnect delay of these examples is obtained with little or no impact on chip area after routing by modifying the placement alone. >
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Citations
Generic global placement and floorplanning
Hans Eisenmann,Frank Johannes +1 more
- 01 May 1998
TL;DR: The algorithm is capable of addressing the problems of global placement, floorplanning, timing minimization and interaction to logic synthesis, and its iterative nature assures that timing requirements are precisely met.
411
Patent
Timing-driven global placement based on geometry-aware timing budgets
Jun-Dong Cho,David S. Kung +1 more
- 11 Apr 2001
TL;DR: In this paper, a timing budget management technique which satisfies triangle parity and inequality, a timing-driven quadrisection placement strategy based on flexible timing window configurations to minimize the wirelength and congestion during each mincut quad-partition of top-down hierarchy, and a linear programming formulation incorporating bin capacity, channel capacity and congestion criticality.
131
RITUAL: a performance driven placement algorithm for small cell ICs
Arvind Srinivasan,Kamal Chaudhary,Ernest S. Kuh +2 more
- 11 Nov 1991
TL;DR: An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described and yields very good results, as is shown on a set of real examples.
119
SPEED: fast and efficient timing driven placement
B.M. Riess,G.G. Ettelt +1 more
- 28 Apr 1995
TL;DR: A timing driven placement approach for very large circuits is described, and results of benchmark circuits with up to 25,000 cells show an excellent quality in terms of maximum path delay and total area after final routing.
89
Patent
Optimizing integrated circuit design through use of sequential timing information
Christoph Albrecht,Philip Chong,Andreas Kuehlmann,Ellen M. Sentovich,Roberto Passerone +4 more
- 02 May 2007
TL;DR: In this paper, a method for determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design is provided, wherein the critical cycles is a cycle in the design that has the highest proportionality of delay to number of registers.
89
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