Book Chapter10.1007/978-3-319-23479-3_5
Reversible Sequential Logic Circuits
Saleem M. R. Taha
- 01 Jan 2016
- pp 119-134
TL;DR: The first work to design reversible sequential circuits is in 2005, and the majority of work has limited itself to combinational logic.
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Abstract: Recent work has begun to investigate the advantages of using reversible logic for the design of circuits. The majority of work, however, has limited itself to combinational logic. Researchers are recently beginning to suggest possibilities for sequential implementations [1]. As far as it can be discovered (due to the survey of literature) the first work to design reversible sequential circuits is in 2005 [2].
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References
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TL;DR: A new generation of predictive technology model (PTM) is developed, covering emerging physical effects and alternative structures, based on physical models and early stage silicon data, and correctly captures process sensitivities in the nanometer regime.
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A beginning in the reversible logic synthesis of sequential circuits
Himanshu Thapliyal,M. B. Srinivas,Mark Zwolinski +2 more
- 07 Sep 2005
TL;DR: In this paper, the initial threshold to building a more complex system having reversible sequential circuits as a primitive component and which can execute more complicated operations using quantum computers has been provided and the reversible circuits form the basic building block of quantum computers as all quantum operations are reversible.
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- 21 May 2006
TL;DR: This work presents an analysis of a basic memory element, the RS-latch, and a number of possible implementations, and introduces four reversible flip-flop designs based on the reversible RS- latch implementation.
Synthesis of Reversible Sequential Elements
Min-Lun Chuang,Chun-Yao Wang +1 more
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TL;DR: This work presents novel designs of reversible sequential elements such as D latch, JK latch, and T latch, based on these reversible latches, and the designs of the corresponding flip-flops.
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- 06 Aug 2006
TL;DR: In this article, the authors proposed the use of reversible logic for designing the ALU of a cryptosystem to prevent differential power analysis (DPA) attacks, which is a major challenge to mathematically secure cryptographic protocols.