Resource Based Optimization for Simultaneous Shield and Repeater Insertion
TL;DR: A new approach for resource based optimization for high performance integrated circuits is presented, resulting in minimum coupling noise under power, delay, and area constraints.
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Abstract: A new approach for resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum coupling noise under power, delay, and area constraints. Design expressions exhibiting parabolic noise behavior are compared with SPICE simulations. Due to the parabolic coupled noise behavior, the minimum noise is established. A design case is compared with only shielding and only repeater insertion techniques, exhibiting enhanced performance for different resources.
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Figures
Fig. 5. Top view of Fig. 4. The lighter color represents a larger amount of noise. 
TABLE I THREE DESIGN CASES SHOWN IN FIG. 7 AND EVALUATED IN SPICE 
Fig. 8. , , and as a function of power at the maximum delay (350 ps) and area (4.15 nm ). 
Fig. 6. Noise as a function of delay at a constant power (50 W) and maximum allowed area (4.15 nm ). 
Fig. 7. Noise as a function of power at the maximum allowed delay (350 ps) and area (4.15 nm ). 
Fig. 1. Optimization flow diagram. (a) Standard and (b) resource based optimization processes.
Citations
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TL;DR: In this paper, the optimal number of repeaters to be inserted along a resistive interconnect line for reduced delay is analyzed. And the analytical model used in these design equations is based on the /spl alpha/-power law I-V equations for modeling short channel devices and exhibits a maximum error of 16% for typical RC loads as compared to SPICE.
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