Refresh control system

TL;DR: In this paper, the authors propose to prevent erasure of information stored into a dynamic memory cell always surely by performing refresh operation automatically with a refresh controller at the time of test mode.

Abstract: PURPOSE:To prevent erasion of information stored into a dynamic memory cell always surely by performing refresh operation automatically with a refresh controller at the time of test mode. CONSTITUTION:Normally, a refresh controller 7 is operated by the microcommand stored into a control store 1. On the other hand, at the time of test mode, the test mode signal 8 of an input terminal 9 causes a controller 7 to automatically start the refresh operation by a built-in timer 10. The timer 10 excecutes the refreshing of a dynamic memory 4 at the refresh cycle time similar to that in the normal time. In this case, the clock applied to the store 1 and a microprocessor 3 is stopped temporarily, and if the period of the clock is sufficiently long and the accessing into the memory 4 may be executed twice in one clock, the accessing from the processor 3 and the refresh cycle from the controller 7 are processed time dividedly during clock.