Open AccessJournal Article
Reduction of Leakage Current in Tristate Inverter Using High-K Dielectric
Ankit Kumar Katare,Monika Kapoor +1 more
TL;DR: In CMOS applications as device scaling, obeying Moore's law reduces the active area of the devices to nearly atomic dimensions The high-k dielectrics need to be used to prevent the tunneling effects which increase the leakage currents as discussed by the authors.
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Abstract: In CMOS applications as device scaling, obeying Moore’s law reduces the active area of the devices to nearly atomic dimensions The high-k dielectrics need to be used to prevent the tunneling effects which increase the leakage currents In recent years, several emerging high-k materials have attracted enormous attention as potential candidates for electronic devices Silicon dioxide (SiO2) has been used as dielectric for more than 40 years because of its manufacturability and ability to deliver continued transistor performance improvements as it has been made ever thinner Among the many potential high-k materials, LaAlO3 has recently attracted much attention due to its many advantages such as high dielectric constant, high bandgap, and amorphous structure up to high temperatureIn CMOS applications as device scaling, obeying Moore’s law reduces the active area of the devices to nearly atomic dimensions The high-k dielectrics need to be used to prevent the tunneling effects which increase the leakage currents In recent years, several emerging high-k materials have attracted enormous attention as potential candidates for electronic devices Silicon dioxide (SiO2) has been used as dielectric for more than 40 years because of its manufacturability and ability to deliver continued transistor performance improvements as it has been made ever thinner Among the many potential high-k materials, LaAlO3 has recently attracted much attention due to its many advantages such as high dielectric constant, high bandgap, and amorphous structure up to high temperature
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References
Multiple-gate SOI MOSFETs
TL;DR: In this paper, the authors describe the evolution and properties of a new class of MOSFETs, called triple-plus (3 + )-gate devices, which offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOS-FET.
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Influence of device engineering on the analog and RF performances of SOI MOSFETs
Valeriya Kilchytska,Amaury Nève,Laurent Vancaillie,David Levacq,Stéphane Adriaensen,H. van Meer,K. De Meyer,C. Raynaud,Morin Dehan,Jean-Pierre Raskin,Denis Flandre +10 more
TL;DR: In this paper, the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m.
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Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs
TL;DR: This paper investigates the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications and shows improvements in gate- and channel-engineered devices.
197
Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering
TL;DR: In this article, two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology and two-dimensional (2D) numerical simulations reveal that the hetero-material gate field effect transistor (HMGFET) demonstrates extended threshold voltage roll-off to much smaller length and shows simultaneous transconductance enhancement and suppression of short-channel effects.
Impact of High- $k$ Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs
C.R. Manoj,Valipe Ramgopal Rao +1 more
TL;DR: In this paper, the impact of high-k gate dielectrics on device short-channel and circuit performance of fin field effect transistors is studied over a wide range of dielectric permittivities.
101