Proceedings Article10.1109/IEDM.2005.1609317
Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies
Sungjae Lee,Lawrence F. Wagner,Basanth Jagannathan,Sebastian Csutak,John J. Pekarik,Matthew J. Breitwisch,R. Ramachandran,Gregory G. Freeman +7 more
- 05 Dec 2005
- pp 241-244
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TL;DR: In this article, the effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX, in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm.
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Abstract: We report record RF FET performance in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm and analyze factors contributing to that performance The effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX A peak fT of 330 GHz is measured in a fully-wired 65-nm NFET A complete de-embedding method to accurately determine RF characteristics of the intrinsic 90-nm SOI NFET results in a peak fT of 290 GHz and an fMAX of 450 GHz
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Citations
Ge-on-SOI-Detector/Si-CMOS-Amplifier Receivers for High-Performance Optical-Communication Applications
Steven J. Koester,Clint L. Schow,Laurent Schares,G. Dehlinger,Jeremy D. Schaub,Fuad E. Doany,Richard A. John +6 more
- 01 Jan 2007
TL;DR: An overview and assessment of high-performance receivers based upon Ge-on-silicon-oninsulator (Geon-SOI) photodiodes and Si CMOS amplifier ICs is provided in this paper.
91
Analog/RF Performance of Multichannel SOI MOSFET
Tao Chuan Lim,E. Bernard,O. Rozeau,Thomas Ernst,Bernard Guillaumot,N. Vulliet,C. Buj-Dufournet,M. Paccaud,Sylvie Lepilliet,Gilles Dambrine,Francois Danneville +10 more
TL;DR: In this article, a 3-D multichannel SOI MOSFET (MCFET) with a gate length of 50 nm is presented, and the sensitivity of the spacer length to the RF/analog performances is experimentally analyzed and validated using ac simulation.
51
Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit
M. K. Md Arshad,Valeriya Kilchytska,Mostafa Emam,Francois Andrieu,Denis Flandre,Jean-Pierre Raskin +5 more
TL;DR: In this paper, the harmful effect of parasitic resistances and capacitances on RF figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) FD SOI n-MOSFETs is discussed.
40
A W-Band LNA/Phase Shifter With 5-dB NF and 24-mW Power Consumption in 32-nm CMOS SOI
TL;DR: In this paper, a W-band phased array receive front end in 32-nm CMOS silicon-on-insulator technology is presented, which is based on cascode low-noise amplifiers and passive switched LC 5-bit phase-shifters.
36
Microwave Noise and FET Devices
TL;DR: In this paper, a short presentation of available FET technologies (GaAs MESFET, ΠI-V HEMT, and silicon CMOS) has been presented.
31
References
A Four-Step Method for De-Embedding Gigahertz
Troels Emil Kolding
- 01 Jan 2000
TL;DR: The proposed de-embedding method addresses issues of substrate coupling and contact effects and is therefore suitable for measurements with lossy technologies such as CMOS and allows large devices to be measured with high accuracy.
179
Comparison of the "pad-open-short" and "open-short-load" deembedding techniques for accurate on-wafer RF characterization of high-quality passives
TL;DR: In this paper, the impedance errors remaining after applying the industry standard "open short," a "pad-open-short," and a "Open Shortload" deembedding scheme on a 0.43-nH 20-GHz high-Q single-loop inductor test structure are investigated using real S-parameter data taken up to 50 GHz.
131
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
Effendi Leobandung,H. Nayakama,Dan Mocuta,K. Miyamoto,M. Angyal,H.V. Meer,K. McStay,Ishtiaq Ahsan,Scott D. Allen,Atsushi Azuma,Michael P. Belyansky,R.-V. Bentum,J. Cheng,Dureseti Chidambarrao,B. Dirahoui,M. Fukasawa,M. Gerhardt,Michael A. Gribelyuk,Scott Halle,H. Harifuchi,D. Harmon,J. Heaps-Nelson,H. Hichri,K. Ida,M. Inohara,I.C. Inouc,Keith Jenkins,T. Kawamura,Byeong Y. Kim,S.-K. Ku,Mahender Kumar,S. Lane,Lars W. Liebmann,R. Logan,I. Melville,K. Miyashita,Anda Mocuta,P. O'Neil,M.-F. Ng,Takeshi Nogami,A. Nomura,Christine Norris,E. Nowak,Mizuki Ono,Siddhartha Panda,C. Penny,Carl J. Radens,Ravikumar Ramachandran,A. Ray,S.-H. Rhee,D. Ryan,T. Shinohara,G. Sudo,F. Sugaya,Jay W. Strane,Y. Tan,L. Tsou,L. K. Wang,F. Wirbeleit,S. Wu,Tenko Yamashita,H. Yan,Q. Ye,D. Yoneyama,D. Zamdmer,Huicai Zhong,Huilong Zhu,Wenjuan Zhu,Paul D. Agnello,Scott J. Bukofsky,Gary B. Bronner,Emmanuel F. Crabbe,G. Freeman,Shih-Fen Huang,T. Ivers,H. Kuroda,D. McHerron,J. Pellerin,Yoshiaki Toyoshima,S. Subbanna,N. Kepler,L. Su +81 more
- 14 Jun 2005
TL;DR: In this article, a high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels.
76
Overlooked interfacial silicide-polysilicon gate resistance in MOS transistors
TL;DR: In this paper, a previously overlooked gate resistance component in silicided polysilicon-gate metal-oxide-semiconductor field effect transistors (MOSFETs) is discussed.
53
Record RF performance of standard 90 nm CMOS technology
L.F. Tiemeijer,R.J. Havens,R. de Kort,A.J. Scholten,R. van Langevelde,D.B.M. Klaassen,Guido T. Sasse,Y. Bouttement,C. Petot,Serge Bardy,Daniel Gloria,Patrick Scheer,S. Boret,B. Van Haaren,C. Clement,J.-F. Larchanche,I.-S. Lim,A. Duvallet,A. Zlotnicka +18 more
- 13 Dec 2004
TL;DR: In this article, the authors optimized three key RF devices realized in standard logic 90 nm CMOS technology and reported a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.
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