Patent
Reconfigurable memory system
Robert R. Trottier,James B Macdonald,John M. Martins,Dennis J. Kayser +3 more
- 09 Jan 1984
66
TL;DR: In this paper, an address translator provides addresses addressing M banks in parallel, so that M locations are read in each read operation, and a bus reconfiguration multiplexer which reconfigures the bank output busses in parallel and selects one or more bank outputs as the memory output to the system processor.
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Abstract: Apparatus and method for reconfiguring a memory in a data processing system to increase the rate of information transfer between system memory and processor. The system memory is comprised of a plurality M of memory banks, each having a separate data output path. In a first configuration a memory controller addresses the memory banks sequentially to read from one address location at a time. The memory is reconfigured by an address translator providing addresses addressing M banks in parallel, so that M locations are read in each read operation, and a bus reconfiguration multiplexer which reconfigures the bank output busses in parallel and selects one or more bank output busses as the memory output to the system processor. In a further embodiment, a cache is connected in parallel with the parallel bank outputs for storing information appearing upon the non-selected bank output busses paths for subsequent transfer to the memory output in a subsequent reading from memory of previously read but non-selected information.
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Citations
Patent
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TL;DR: In this paper, an integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices using a single fly-by (or bus) signal path.
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TL;DR: In this article, an MPEG-video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine is described. But the authors do not specify the corresponding decoding circuits.
129
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Patent
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