Quantum Mechanical Corrected Simulation Program with Integrated Circuit Emphasis Model for Simulation of Ultrathin Oxide Metal-Oxide-Semiconductor Field Effect Transistor Gate Tunneling Current

TL;DR: In this article, a quantum mechanical gate tunneling current model for simulating ultrathin oxide metal-oxide-semiconductor (MOS) devices is presented. And the gate leakage current on the drain current without any numerical convergence problem.

Abstract: In this paper we present a quantum mechanical corrected gate tunneling current model for simulating ultrathin oxide metal-oxide-semiconductor (MOS) devices. By approximating the physically based Esaki-Tsu tunneling formula and explicitly modeling the classical (CL) and quantum mechanical (QM) corrected surface potential, this model successfully predicts the gate tunneling current for ultrathin oxide MOS samples under different applied biases. Simply assuming all tunneling electrons have the same kinetic energy, the Esaki-Tsu tunneling formula is first simplified so that it can be solved without encountering numerical integral problems. Numerical solutions of the classical Poisson equation and Schrodinger-Poisson equations are then used to analytically express the CL and QM corrected surface potentials explicitly in terms of substrate doping, thickness of the gate oxide (Tox), and applied bias. The full explicit, physical-based, and QM corrected gate tunneling current model quantitatively shows good agreement with the technology computer-aided design (TCAD) simulation. Compared with the measured gate tunneling current from fabricated 0.12 µm n-type Metal-Oxide-Semiconductor Field Effect Transistors (NMOSFETs) with three different thicknesses of gate oxide, Tox=1, 1.2 and 1.5 nm, the QM corrected gate tunneling current model shows good accuracy for various ultrathin oxide samples under different biases. However, the gate tunneling current model with the CL surface potential results in one order of magnitude underestimation in comparison with the measured data. We implement the gate tunneling current model into the simulation program with integrated circuit emphasis (SPICE) simulator and perform a DC simulation. Simulated results preliminarily show the effect of the gate leakage current on the drain current without any numerical convergence problem.