Patent
Protocol for communication with dynamic memory
Richard M. Barth,Frederick Abbot Ware,John B. Dillon,Donald C. Stark,Craig E. Hampel,Matthew Murdy Griffin +5 more
- 18 Oct 1996
210
TL;DR: In this paper, a system and method for performing data transfers within a computer system is presented, which includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed.
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Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.
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Citations
Patent
Methods and apparatuses for programming user-defined information into electronic devices
Michael E. Shanahan
- 21 Dec 2012
TL;DR: In this paper, a device for programming user-defined information into an electronic device is provided, allowing a user to program customized information, such as user-selected audio, video, or Internet access information into his or her programmable device.
314
Patent
Asynchronous interface for a nonvolatile memory
Duane R. Mills,Brian Lyn Dipert,Sachidanandan Sambandan,Bruce McCormick,Richard D. Pashley +4 more
- 18 Jun 1997
TL;DR: In this article, a flash memory chip that can be switched into four different read modes is described, including synchronous flash, asynchronous DRAM, and standard DRAM read and write modes.
266
Patent
Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
Brent Keeth
- 09 Sep 1998
TL;DR: In this paper, a method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signals to store the digital signal responsive to the clock signal.
257
Patent
Methods and apparatus of stacking DRAMs
Suresh Natarajan Rajan,Michael John Sebastian Smith,David T. Wang +2 more
- 01 Sep 2006
TL;DR: In this paper, large capacity memory systems are constructed using stacked memory integrated circuits or chips, which are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
245
Patent
Clock vernier adjustment
Brent Keeth
- 03 Dec 1997
TL;DR: In this article, a memory system with a memory controller coupled to memory modules through data and command busses is described. But it does not specify the memory controller's role.
228
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Michael Farmwald,Mark Horowitz +1 more
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TL;DR: In this article, the authors present a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address.
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Patent
Synchronous semiconductor memory device
Yasuhiro Konishi,Takayuki Miyamoto,Takeshi Kajimoto,Hisashi Iwamoto +3 more
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TL;DR: In this paper, the memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the global IO lines connect to preamplifier groups and to write buffer groups.
298
Patent
Apparatus for synchronously generating clock signals in a data processing system
Michael Farmwald,Mark Horowitz +1 more
- 05 Mar 1992
TL;DR: In this paper, an apparatus for synchronously generating a first clock signal and a second clock signal in a second circuitry of a data processing system is described, where a clock generating circuitry generates a global clock signal.
227
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC
Howard Leo Kalter,C.H. Stapper,John E. Barth,J. Dilorenzo,Charles Edward Drake,John A. Fifield,Gordon Arthur Kelley,Scott C. Lewis,W.B. van der Hoeven,James Andrew Yankosky +9 more
TL;DR: A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described.
184
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