Patent
Programmable Transistor Array Design Methodology
Oscar M. K. Law,Kuo H. Wu +1 more
- 12 Nov 2009
30
TL;DR: In this article, a method of designing integrated circuits includes providing a first chip and a second chip identical to each other, each of which includes a base layer including a Logic Transistor Unit (LTU) array.
read more
Abstract: A method of designing integrated circuits includes providing a first chip and a second chip identical to each other. Each of the first chip and the second chip includes a base layer including a Logic Transistor Unit (LTU) array. The LTU array includes LTUs identical to each other and arranged in rows and columns. The method further includes connecting the base layer of the first chip to form a first application chip; and connecting the base layer of the second chip to form a second application chip different from the first application chip.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
- 28 Jun 2011
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
413
Patent
3D semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Deepak C. Sekar +2 more
- 27 Mar 2017
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
185
Patent
3d semiconductor device
Zvi Or-Bach,Zeev Wurman +1 more
- 07 Nov 2010
TL;DR: In this paper, a semiconductor device comprising first layer comprising multiplicity of first transistors and second layer consisting multiplicityof second transistors is defined, and at least one function constructed by the first transistor is structure so it could be replaced by a function created by the second transistor.
48
Patent
Power routing in standard cell designs
Deepak D. Sherlekar
- 27 Mar 2012
TL;DR: A cell-based architecture for an integrated circuit is described in this article, where a row of cell instances borders a first adjacent row of cells along a first boundary and a second adjacent cell instance along a second boundary.
37
Patent
Pin routing in standard cells
Deepak D. Sherlekar,Vahe Hovsepyan +1 more
- 23 Mar 2011
TL;DR: In this article, the authors describe a set of cells that are designed to accommodate metal routing tracks having a pitch that is an odd multiple of a manufacturing grid and include cell pins that are located within the cell based on the offsets of the routing tracks relative to the cell boundaries.
36
References
Patent
Semiconductor integrated circuit and method of designing the same
Tsuguo Kobayashi
- 06 Apr 2004
TL;DR: In this paper, a semiconductor integrated circuit has a cell region in which a plurality of MOS transistors forming at least one cell are placed; and first and second power lines placed along one direction in a peripheral portion of the cell region, wherein in the cell regions, gate grids for defining a first pitch in the one direction and pin grids for defined a second pitch in one direction are set.
86
Patent
Molecular field programmable gate array
James Lyke
- 01 Sep 1999
TL;DR: In this article, an architectural concept for field programmable gate array circuits is presented based on a universal fabric of cells called look-up tables arranged in a direct, repeatable spatial grid.
55
Patent
Metal programmed transistor array
Daren Allee
- 03 Feb 1995
TL;DR: In this article, the use of a transistor at specific row and column intersections is controlled by controlling whether the column connects electrically with the drain implant of the transistor. But, the transistor is not connected to the metal layer above through a window in the oxide material.
22
Patent
Adjustable global tap voltage to improve memory cell yield
Vasisht Mantra Vadi
- 18 Mar 2005
TL;DR: In this article, a system that increases device yield by correcting improper operation of the memory cells due to process variations is described, where an array of memory cells and an adjustable bias voltage circuit are coupled to a test circuit that generates a feedback signal indicating whether one or more of the cells fail to operate properly.
21
Patent
Programmable logic devices with silicon-germanium circuitry and associated methods
Ashok K. Kapoor
- 15 Oct 2003
TL;DR: A programmable logic device (PLD) includes programmable electronic circuitry as mentioned in this paper, which may include a variety of configurable or PLC circuitry, including a memory circuitry coupled to the PLC.
12