Journal Article10.1021/acs.nanolett.3c04073
Programmable Threshold Logic Implementations in a Memristor Crossbar Array.
Sang Mo Youn,Jungjin Lee,Sungjoon Kim,Jinwoo Park,Kyuree Kim,Hyungjin Kim +5 more
- 12 Mar 2024
10
TL;DR: Programmable threshold logic implementations in a memristor crossbar array demonstrate accurate programming characteristics and enable reliable operations using read-based logic operations.
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Abstract: In this study, we demonstrate the implementation of programmable threshold logics using a 32 × 32 memristor crossbar array. Thanks to forming-free characteristics obtained by the annealing process, its accurate programming characteristics are presented by a 256-level grayscale image. By simultaneous subtraction between weighted sum and threshold values with a differential pair in an opposite way, 3-input and 4-input Boolean logics are implemented in the crossbar without additional reference bias. Also, we verify a full-adder circuit and analyze its fidelity, depending on the device programming accuracy. Lastly, we successfully implement a 4-bit ripple carry adder in the crossbar and achieve reliable operations by read-based logic operations. Compared to stateful logic driven by device switching, a 4-bit ripple carry adder on a memristor crossbar array can perform more reliably in fewer steps thanks to its read-based parallel logic operation.
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Citations
Complex Dynamical Behavior of Locally Active Discrete Memristor-Coupled Neural Networks with Synaptic Crosstalk: Attractor Coexistence and Reentrant Feigenbaum Trees
D. Liu,Kaihua Wang,Yinghong Cao,Jinshi Lu +3 more
TL;DR: Numerical and experimental findings show that the synaptic connections of neurons can be modeled by discrete memristor coupling which leads to the construction of more complicated discrete neural networks.
Coupling-Free Readout Scheme for Memcapacitors With NAND Flash Structure
Suhyeon Ahn,Junsu Yu,Hwiho Hwang,Min Song,Dongjin Yu -,Sungmin Hwang,In Young Chung,Woo Young Choi,Hyungjin Kim +8 more
TL;DR: A coupling-free readout scheme designed for a hardware neural network employing memcapacitive devices based on Si MOS capacitors having a charging trapping layer is proposed, mitigating the issue of additional bitline (BL) charge accumulation caused by coupling effects.
Memristor Crossbar Array with Enhanced Device Yield for In-Memory Vector–Matrix Multiplication
Tae‐Hyeon Kim,Sung-Joon Kim,Jin‐Woo Park,Sangwook Youn,Hyungjin Kim +4 more
TL;DR: High-yield memristor crossbar array with enhanced device yield for in-memory vector–matrix multiplication. Optimized fabrication process and device design achieve over 98% yield and enable efficient in-memory computing applications.
True random number generator using stochastic noise signal of memristor with variation tolerance
Dongsheng Yu,Suhyeon Ahn,Sangwook Youn,Jinwoo Park,Hyungjin Kim +4 more
Neuron Circuit Based on a Split-gate Transistor with Nonvolatile Memory for Homeostatic Functions of Biological Neurons
H. J. Kim,Sung Yun Woo,Hyungjin Kim +2 more
TL;DR: A neuron circuit based on a split-gate transistor with nonvolatile memory successfully mimics the homeostatic functions of biological neurons. The circuit utilizes a charge trap layer to adjust the threshold voltage and generate a program/erase pulse. The results demonstrate improved recognition rate in a 2-layer SNN.
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