Patent
Programmable sequential logic
Ralph F. Spencer
- 30 Apr 1969
66
TL;DR: In this paper, a mass production sequential logic circuit which can be custom programmed by modification of a single fabrication mask to perform sequential combinational logic is disclosed, which includes a first programmable matrix of voltage controlled devices for generating product terms, a second programmable array of voltage control devices for summing the product terms and a plurality of binary storage elements such as flip-flops or shift registers, input inverters and output buffers on the same semiconductor substrate.
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Abstract: A mass production sequential logic circuit which can be custom programmed by modification of a single fabrication mask to perform sequential combinational logic is disclosed. The circuit includes a first programmable matrix of voltage controlled devices for generating product terms, a second programmable matrix of voltage controlled devices for summing the product terms, a plurality of binary storage elements such as flip-flops or shift registers, input inverters and output buffers on the same semiconductor substrate. The outputs of the second matrix are applied either to the inputs of the storage elements, or to the output buffers, or both. The outputs of the storage elements are applied either to inputs of the first matrix, or to output buffers, or both.
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Citations
Patent
Programmable logic array device using EPROM technology
Robert F. Hartmann,Sau-Ching Wong,Yiu-Fai Chan,Jung-Hsing Ou +3 more
- 03 May 1985
TL;DR: The programmable logic array (PLA) as discussed by the authors is a programmable AND array with a plurality of memory cells arranged in addressable rows (40-45) and columns (32-38) and can be individually programmed to contain logic data.
323
Patent
Programmable logic device with array blocks connected via a programmable interconnect array
Sau-Ching Wong,Hock-Chuen So,Stanley John Kopec,Robert F. Hartmann +3 more
- 23 Feb 1989
TL;DR: In this paper, a programmable logic device having a rela-tively small number of programmable product terms (OE, SETN,P0,P1,P2,INV,ACLK,CLEARN) feeding each fixed combinatorial logic device (51), and additional "expander" programmable P-terms (EXP1,EXP2) which do not directly feed a fixed device.
238
Patent
Programmable logic device
John E. Turner,David L. Rutledge +1 more
- 04 Mar 1985
TL;DR: In this article, an improved programmable logic device (PLD) is described, which employs electrically erasable memory cells which can be programmed and erased at high speed by Fowler-Nordheim tunneling.
203
Patent
Programmable interface for computer system peripheral circuit card
Stanley John Kopec,Yiu-Fai Chan,Robert F. Hartmann +2 more
- 06 Jul 1989
TL;DR: In this article, a programmable interface for a peripheral circuit card is provided, which can be customized by a user for a particular card design, instead of designing a custom interface chip, the designer can program one or more programmable logic devices on the interface chip to interface with whatever devices are on the peripheral circuit cards.
186
Patent
Programmable logic device with array blocks with programmable clocking
Sau-Ching Wong,Hock-Chuen So,Stanley John Kopec,Robert F. Hartmann +3 more
- 14 Sep 1989
TL;DR: In this paper, a programmable logic device has a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device.
144