Programmable MISR modules for logic BIST based VLSI testing

TL;DR: This paper focus on the design of Programmable MISR(Multiple Input Signature Register) modules for Logic BIST based Very Large Scale Integration(VLSI) Integrated Circuit(IC) testing.

Abstract: This paper focus on the design of Programmable MISR(Multiple Input Signature Register) modules for Logic BIST based Very Large Scale Integration(VLSI) Integrated Circuit(IC) testing. The advancement in VLSI technology have made chip testing more complicated which has lead to the popularity of Logic Built In Self Test(LBIST) compared to Automatic Test Equipment(ATE). Logic BIST allows in-built chip testing with the help of an additional hardware structure inside the circuit. The test patterns are not applied by ATE but are generated by inbuilt testing circuits. MISR is commonly used as an output response analyzer since it is alternative to n-parallel LFSRs. MISRs accelerates the testing methodology by compacting multi-bit streams into single signature. A Reconfigurable LFSR can be used as the test pattern generator as well as a response compactor inside Logic BIST to improve the fault coverage of IC testing. The proposed MISR architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 64) programmable MISR structures is synthesized in Xilinx Spartan 6 for implementing MISR on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete MISR are implemented. All the designs are synthesized for ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable designs are analyzed for speed, power and area.