Patent
Programmable logic array having a changeable logic structure
Harufusa Kondou,Hiroshi Kuranaga +1 more
- 10 Nov 1988
102
TL;DR: In this article, a Programmable Logic Array (PLA) cells are arranged at intersections of input lines and output lines of the array and switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.
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Abstract: Programmable Logic Array PLA) cells are arranged at intersections of input lines and output lines of the array. Particular PLA cells to be programmed are arbitrarily selected by word line and bit line decoders. Switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.
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Citations
Patent
Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
Kent L. Gilson
- 11 Dec 1992
TL;DR: In this article, an integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA), which is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit.
346
Patent
A programmable logic device which stores more than one configuration and means for switching configurations
Randy T. Ong
- 22 Apr 1995
TL;DR: In this paper, a programmable logic device includes a configuration memory expanded to store two or more complete sets of configuration data, which can be re-configured within a user's clock cycle.
334
Patent
Emulation system with time-multiplexed interconnect
Stephen P. Sample,Mikhail Bershteyn,Michael R. Butts,Jerry R. Bauer +3 more
- 18 May 1998
TL;DR: In this article, a hardware emulation system is described, which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board, and the logic circuits necessary for executing logic analyzer functions are programmed into programmable resources in the logic chips of the emulation system.
180
Patent
Distributed memory architecture for a configurable logic array and method for using distributed memory
Ross H. Freeman,Hung-Cheng Hsieh +1 more
- 26 Jul 1990
TL;DR: In this paper, a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function is presented, where the memory cells can also be used as memory for access by other parts during operation.
156
Patent
Converification system and method
Sharon Sheau-Pyng Lin,Ping-sheng Tseng +1 more
- 12 Jun 1998
TL;DR: In this paper, the authors present a coverification system that includes a reconfigurable computing system (hereinafter RCC computing system) and an external I/O array (herein referred to as RCC hardware array).
153
References
•Book
Introduction to Nmos and Cmos Vlsi Systems Design
Amar Mukherjee
- 01 Jan 1986
TL;DR: This paper describes an efficient and flexible CMOS sea-oi, a particular style of digital circuitry design and the family of processes used to design NMOS and VLSI systems.
148