Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Ana Azevedo,Ilya Issenin,R. Cornea,Rajesh Gupta,Nikil Dutt,Alexander V. Veidenbaum,Alexandru Nicolau +6 more
- 04 Mar 2002
- pp 168-175
TL;DR: This paper introduces a novel intra-task DVS technique under compiler control using program checkpoints, which handles multiple intra- task performance deadlines and modulates power consumption according to a run-time power budget.
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Abstract: Dynamic voltage scaling (DVS) is a known effective mechanism for reducing CPU energy consumption without significant performance degradation. While a lot of work has been done on inter-task scheduling algorithms to implement DVS under operating system control, new research challenges exist in intra-task DVS techniques under software and compiler control. In this paper we introduce a novel intra-task DVS technique under compiler control using program checkpoints. Checkpoints are generated at compile time and indicate places in the code where the processor speed and voltage should be re-calculated. Checkpoints also carry user-defined time constraints. Our technique handles multiple intra-task performance deadlines and modulates power consumption according to a run-time power budget. We experimented with two heuristics for adjusting the clock frequency and voltage. For the particular benchmark studied, one heuristic yielded 63% more energy savings than the other. With the best of the heuristics we designed, our technique resulted in 82% energy savings over the execution of the program without employing DVS.
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Citations
Power reduction techniques for microprocessor systems
TL;DR: It is concluded that power management is a multifaceted discipline that is continually expanding with new techniques being developed at every level and it remains too early to tell which techniques will ultimately solve the power problem.
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Johan Pouwelse,Koen Langendoen,Henk Sips +2 more
- 06 Aug 2001
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Proceedings : 2002 Design, Automation and Test in Europe, conference and exhibition : March 4-8, 2002, Paris, France
Aeia,Carlos Delgado Kloos,Jose da Franca +2 more
- 01 Jan 2002
TL;DR: The following topics are dealt with: semiconductor IP; formal verification; cooling; power management; defect oriented test; SAT and BDD techniques; low power design; mixed signal test; collaborative design; logic synthesis; symbolic techniques; EDA tools; analogue circuits; asynchronous circuits; BIST; DFT.
119
Voltage-clock-scaling adaptive scheduling techniques for low power in hard real-time systems
Chandan Krishna,Y.-H. Lee +1 more
TL;DR: This work shows how voltage scaling can be scheduled to reduce energy usage while still meeting real-time deadlines.
90
Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors
Chung-Hsing Hsu,Ulrich Kremer,Michael S. Hsiao +2 more
- 06 Aug 2001
TL;DR: This paper discusses a compilation strategy that identifies scaling opportunities without significant overall performance penalty and results show CPU energy savings of 3.97%-23.53% for the SPECfp95 benchmark suite.